Merge "Merge remote-tracking branch 'quic/msm-4.14' into dev/msm-4.14-display"...

		/sys/devices/system/cpu/vulnerabilities/meltdown

		/sys/devices/system/cpu/vulnerabilities/spectre_v1

		/sys/devices/system/cpu/vulnerabilities/spectre_v2

		/sys/devices/system/cpu/vulnerabilities/spec_store_bypass

Date:		January 2018

Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>

Description:	Information about CPU vulnerabilities

			allow data leaks with this option, which is equivalent

			to spectre_v2=off.

	nospec_store_bypass_disable

			[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

	noxsave		[BUGS=X86] Disables x86 extended register state save

			and restore using xsave. The kernel will fallback to

			enabling legacy floating-point and sse state.

			Not specifying this option is equivalent to

			spectre_v2=auto.

	spec_store_bypass_disable=

			[HW] Control Speculative Store Bypass (SSB) Disable mitigation

			(Speculative Store Bypass vulnerability)

			Certain CPUs are vulnerable to an exploit against a

			a common industry wide performance optimization known

			as "Speculative Store Bypass" in which recent stores

			to the same memory location may not be observed by

			later loads during speculative execution. The idea

			is that such stores are unlikely and that they can

			be detected prior to instruction retirement at the

			end of a particular speculation execution window.

			In vulnerable processors, the speculatively forwarded

			store can be used in a cache side channel attack, for

			example to read memory to which the attacker does not

			directly have access (e.g. inside sandboxed code).

			This parameter controls whether the Speculative Store

			Bypass optimization is used.

			on      - Unconditionally disable Speculative Store Bypass

			off     - Unconditionally enable Speculative Store Bypass

			auto    - Kernel detects whether the CPU model contains an

				  implementation of Speculative Store Bypass and

				  picks the most appropriate mitigation. If the

				  CPU is not vulnerable, "off" is selected. If the

				  CPU is vulnerable the default mitigation is

				  architecture and Kconfig dependent. See below.

			prctl   - Control Speculative Store Bypass per thread

				  via prctl. Speculative Store Bypass is enabled

				  for a process by default. The state of the control

				  is inherited on fork.

			seccomp - Same as "prctl" above, but all seccomp threads

				  will disable SSB unless they explicitly opt out.

			Not specifying this option is equivalent to

			spec_store_bypass_disable=auto.

			Default mitigations:

			X86:	If CONFIG_SECCOMP=y "seccomp", otherwise "prctl"

	spia_io_base=	[HW,MTD]

	spia_fio_base=

	spia_pedr=

			remove bandwidth votes.

qcom,disable-ports:	The ports to disable on the sideband manager when the

			requirement bandwidth affecting	the node reduces to 0.

node-reg-names:		Names of the regulator associated with bus node used

			to grab the phandle of the regulator.

Example:

  Value type: Array of <string>

  Definition: Channel names configured in mhi,chan-cfg.

- mhi,ev-cfg

  Usage: required

  Value type: Array of <u32>

  Definition: Array of tuples describe event configuration.

	1st element: Event ring length in elements

	2nd element: Interrupt moderation time in ms

	3rd element: MSI associated with this event ring

	4th element: Dedicated channel number, if it's a dedicated event ring

	5th element: Event ring priority, set to 1 for now

	6th element: Event doorbell mode configuration as defined by

	enum MHI_BRSTMODE

		2 = burst mode disabled

		3 = burst mode enabled

	7th element: Bitwise configuration settings for the channel

		Bit mask:

		BIT(0) : Event ring associated with hardware channels

		BIT(1) : Client manages the event ring (use by napi_poll)

		BIT(2) : Event ring associated with offload channel

		BIT(3) : Event ring dedicated to control events only

- mhi,timeout

  Usage: optional

  Value type: <u32>

  Value type: <u32>

  Definition: Size of each segment to allocate for BHIe vector table

==========================

mhi event node properties:

==========================

- mhi,num-elements

  Usage: required

  Value type: <u32>

  Definition: Number of elements event ring support

- mhi,intmod

  Usage: required

  Value type: <u32>

  Definition: interrupt moderation time in ms

- mhi,msi

  Usage: required

  Value type: <u32>

  Definition: MSI associated with this event ring

- mhi,chan

  Usage: optional

  Value type: <u32>

  Definition: Dedicated channel number, if it's a dedicated event ring

- mhi,priority

  Usage: required

  Value type: <u32>

  Definition: Event ring priority, set to 1 for now

- mhi,brstmode

  Usage: required

  Value type: <u32>

  Definition: Event doorbell mode configuration as defined by

	enum MHI_BRSTMODE

		2 = burst mode disabled

		3 = burst mode enabled

- mhi,data-type

  Usage: optional

  Value type: <u32>

  Definition: Type of data this event ring will process as defined

	by enum mhi_er_data_type

		0 = process data packets (default)

		1 = process mhi control packets

- mhi,hw-ev

  Usage: optional

  Value type: <bool>

  Definition: Event ring associated with hardware channels

- mhi,client-manage

  Usage: optional

  Value type: <bool>

  Definition: Client manages the event ring (use by napi_poll)

- mhi,offload

  Usage: optional

  Value type: <bool>

  Definition: Event ring associated with offload channel

Children node properties:

MHI drivers that require DT can add driver specific information as a child node.

		       <2 64 1 1 2 1 1 0 0>, <3 64 1 2 2 1 1 0 0>;

	mhi,chan-names = "LOOPBACK", "LOOPBACK",

			 "SAHARA", "SAHARA";

	mhi,ev-cfg = <64 1 1 0 1 2 8>

		     <64 1 2 0 1 2 0>;

	mhi_event@0 {

		mhi,num-elements = <32>;

		mhi,intmod = <1>;

		mhi,msi = <1>;

		mhi,chan = <0>;

		mhi,priority = <1>;

		mhi,bstmode = <2>;

		mhi,data-type = <1>;

	};

	mhi_event@1 {

		mhi,num-elements = <256>;

		mhi,intmod = <1>;

		mhi,msi = <2>;

		mhi,chan = <0>;

		mhi,priority = <1>;

		mhi,bstmode = <2>;

	};

	mhi,fw-name = "sbl1.mbn";

	mhi,timeout = <500>;

Example:

wakegic: wake-gic@7781b8 {

	compatible = "qcom,mpm-gic", "qcom,mpm-gic-msm8953";

	compatible = "qcom,mpm-gic", "qcom,mpm-gic-msm8953", "qcom,mpm-gic-msm8937";

	interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;

	reg = <0x601d4 0x1000>,

	    <0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */

Example:

wakegpio: wake-gpio {

	compatible = "qcom,mpm-gpio", "qcom,mpm-gpio-msm8953";

	compatible = "qcom,mpm-gpio", "qcom,mpm-gpio-msm8953", "qcom,mpm-gpio-msm8937";

	interrupt-controller;

	interrupt-parent = <&tlmm>;

	#interrupt-cells = <2>;