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Commit df5f0f0a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 RAS updates from Ingo Molnar:
 "The main changes in this development cycle were:

   - more AMD northbridge support work, mostly in preparation for Fam17h
     CPUs (Yazen Ghannam, Borislav Petkov)

   - cleanups/refactorings and fixes (Borislav Petkov, Tony Luck,
     Yinghai Lu)"

* 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Include the PPIN in MCE records when available
  x86/mce/AMD: Add system physical address translation for AMD Fam17h
  x86/amd_nb: Add SMN and Indirect Data Fabric access for AMD Fam17h
  x86/amd_nb: Add Fam17h Data Fabric as "Northbridge"
  x86/amd_nb: Make all exports EXPORT_SYMBOL_GPL
  x86/amd_nb: Make amd_northbridges internal to amd_nb.c
  x86/mce/AMD: Reset Threshold Limit after logging error
  x86/mce/AMD: Fix HWID_MCATYPE calculation by grouping arguments
  x86/MCE: Correct TSC timestamping of error records
  x86/RAS: Hide SMCA bank names
  x86/RAS: Rename smca_bank_names to smca_names
  x86/RAS: Simplify SMCA HWID descriptor struct
  x86/RAS: Simplify SMCA bank descriptor struct
  x86/MCE: Dump MCE to dmesg if no consumers
  x86/RAS: Add TSC timestamp to the injected MCE
  x86/MCE: Do not look at panic_on_oops in the severity grading
parents cbaa1576 3f5a7896

arch/x86/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -1046,7 +1046,7 @@ config X86_MCE_INTEL 
config X86_MCE_AMD

	def_bool y

	prompt "AMD MCE features"

	depends on X86_MCE && X86_LOCAL_APIC

	depends on X86_MCE && X86_LOCAL_APIC && AMD_NB

	---help---

	   Additional support for AMD specific MCE features such as

	   the DRAM Error Threshold.

arch/x86/include/asm/amd_nb.h

+8 −15
Original line number Diff line number Diff line
@@ -21,6 +21,10 @@ extern int amd_numa_init(void); 
extern int amd_get_subcaches(int);

extern int amd_set_subcaches(int, unsigned long);



extern int amd_smn_read(u16 node, u32 address, u32 *value);

extern int amd_smn_write(u16 node, u32 address, u32 value);

extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);



struct amd_l3_cache {

	unsigned indices;

	u8	 subcaches[4];
@@ -55,6 +59,7 @@ struct threshold_bank { 
};



struct amd_northbridge {

	struct pci_dev *root;

	struct pci_dev *misc;

	struct pci_dev *link;

	struct amd_l3_cache l3_cache;
@@ -66,7 +71,6 @@ struct amd_northbridge_info { 
	u64 flags;

	struct amd_northbridge *nb;

};

extern struct amd_northbridge_info amd_northbridges;



#define AMD_NB_GART			BIT(0)

#define AMD_NB_L3_INDEX_DISABLE		BIT(1)
@@ -74,20 +78,9 @@ extern struct amd_northbridge_info amd_northbridges; 


#ifdef CONFIG_AMD_NB



static inline u16 amd_nb_num(void)

{

	return amd_northbridges.num;

}



static inline bool amd_nb_has_feature(unsigned feature)

{

	return ((amd_northbridges.flags & feature) == feature);

}



static inline struct amd_northbridge *node_to_amd_nb(int node)

{

	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;

}

u16 amd_nb_num(void);

bool amd_nb_has_feature(unsigned int feature);

struct amd_northbridge *node_to_amd_nb(int node);



static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)

{

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ 
#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */



#define X86_FEATURE_INTEL_PPIN	( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_INTEL_PT	( 7*32+15) /* Intel Processor Trace */

#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */

arch/x86/include/asm/mce.h

+10 −13
Original line number Diff line number Diff line
@@ -252,8 +252,10 @@ static inline void cmci_recheck(void) {} 


#ifdef CONFIG_X86_MCE_AMD

void mce_amd_feature_init(struct cpuinfo_x86 *c);

int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);

#else

static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }

static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };

#endif



int mce_available(struct cpuinfo_x86 *c);
@@ -356,28 +358,23 @@ enum smca_bank_types { 
	N_SMCA_BANK_TYPES

};



struct smca_bank_name {

	const char *name;	/* Short name for sysfs */

	const char *long_name;	/* Long name for pretty-printing */

};



extern struct smca_bank_name smca_bank_names[N_SMCA_BANK_TYPES];



#define HWID_MCATYPE(hwid, mcatype) ((hwid << 16) | mcatype)

#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))



struct smca_hwid_mcatype {

struct smca_hwid {

	unsigned int bank_type;	/* Use with smca_bank_types for easy indexing. */

	u32 hwid_mcatype;	/* (hwid,mcatype) tuple */

	u32 xec_bitmap;		/* Bitmap of valid ExtErrorCodes; current max is 21. */

};



struct smca_bank_info {

	struct smca_hwid_mcatype *type;

	u32 type_instance;

struct smca_bank {

	struct smca_hwid *hwid;

	/* Instance ID */

	u32 id;

};



extern struct smca_bank_info smca_banks[MAX_NR_BANKS];

extern struct smca_bank smca_banks[MAX_NR_BANKS];



extern const char *smca_get_long_name(enum smca_bank_types t);

#endif



#endif /* _ASM_X86_MCE_H */

arch/x86/include/asm/msr-index.h

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,10 @@ 
#define EFER_FFXSR		(1<<_EFER_FFXSR)



/* Intel MSRs. Some also available on other CPUs */



#define MSR_PPIN_CTL			0x0000004e

#define MSR_PPIN			0x0000004f



#define MSR_IA32_PERFCTR0		0x000000c1

#define MSR_IA32_PERFCTR1		0x000000c2

#define MSR_FSB_FREQ			0x000000cd