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Commit de8228f6 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "power: qpnp-qg: Limit max FCC value based on QG subtype"

parents 0a08a523 670bc9d9

drivers/power/supply/qcom/qg-core.h

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ struct qpnp_qg { 
	int			ibat_tcss_entry;

	int			soc_tcss;

	int			tcss_entry_count;

	int			max_fcc_limit_ma;

	u32			fifo_done_count;

	u32			wa_flags;

	u32			seq_no;

drivers/power/supply/qcom/qpnp-qg.c

+14 −0
Original line number Diff line number Diff line
@@ -2946,6 +2946,13 @@ static int qg_load_battery_profile(struct qpnp_qg *chip) 
		chip->bp.fastchg_curr_ma = -EINVAL;

	}



	/*

	 * Update the max fcc values based on QG subtype including

	 * error margins.

	 */

	chip->bp.fastchg_curr_ma = min(chip->max_fcc_limit_ma,

					chip->bp.fastchg_curr_ma);



	rc = of_property_read_u32(profile_node, "qcom,qg-batt-profile-ver",

				&chip->bp.qg_profile_version);

	if (rc < 0) {
@@ -3317,6 +3324,8 @@ static int qg_sanitize_sdam(struct qpnp_qg *chip) 
}



#define ADC_CONV_DLY_512MS		0xA

#define IBAT_5A_FCC_MA			4800

#define IBAT_10A_FCC_MA			9600

static int qg_hw_init(struct qpnp_qg *chip)

{

	int rc, temp;
@@ -3330,6 +3339,11 @@ static int qg_hw_init(struct qpnp_qg *chip) 
		return rc;

	}



	if (chip->qg_subtype == QG_ADC_IBAT_5A)

		chip->max_fcc_limit_ma = IBAT_5A_FCC_MA;

	else

		chip->max_fcc_limit_ma = IBAT_10A_FCC_MA;



	rc = qg_set_wa_flags(chip);

	if (rc < 0) {

		pr_err("Failed to update PMIC type flags, rc=%d\n", rc);