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Commit de0c9077 authored by Chandana Kishori Chiluveru's avatar Chandana Kishori Chiluveru
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ARM: dts: msm: Add dtsi entries of QMP PHY and QUSB2PHY for ATOLL 



This change adds dtsi node for QMP PHY and QUSB2PHY,
Add macro definitions in a dt-bindings header file for all
the QMP USB DP register offsets. Also adds extcon handles to
support USB type-c or uAB connectors on ATOLL. In case of uAB
connector charger driver provides extcon notifications whereas
for Type-C connector case PD driver provides extcon notifications.

Change-Id: I97904882be2d082494b456b032e7eecae6a2384b
Signed-off-by: default avatarChandana Kishori Chiluveru <cchiluve@codeaurora.org>
parent 5542ee99

arch/arm64/boot/dts/qcom/atoll-usb.dtsi

+242 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include <dt-bindings/clock/qcom,gcc-atoll.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/phy/qcom,atoll-qmp-usb3.h>



&soc {

	usb0: ssusb@a600000 {
@@ -28,6 +29,7 @@ 
		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		USB3_GDSC-supply = <&usb30_prim_gdsc>;

		dpdm-supply = <&qusb_phy0>;

		qcom,use-pdc-interrupts;



		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -81,10 +83,12 @@ 
			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;



		qcom,default-bus-vote = <2>; /* use svs bus voting */

		dwc3@a600000 {

			compatible = "snps,dwc3";

			reg = <0x0a600000 0xcd00>;

			interrupts = <0 133 0>;

			usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,dis_u2_susphy_quirk;
@@ -127,4 +131,242 @@ 
			};

		};

	};



	/* Primary USB port related QUSB2 PHY */

	qusb_phy0: qusb@88e2000 {

		compatible = "qcom,qusb2phy-v2";

		reg = <0x088e2000 0x400>,

			<0x00780200 0x4>,

			<0x088e7014 0x4>;

		reg-names = "qusb_phy_base", "efuse_addr",

				"refgen_north_bg_reg_addr";



		qcom,efuse-bit-pos = <25>;

		qcom,efuse-num-bits = <3>;

		vdd-supply = <&pm6150_l4>;

		vdda18-supply = <&pm6150_l11>;

		vdda33-supply = <&pm6150_l17>;

		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,qusb-phy-reg-offset =

			<0x240 /* QUSB2PHY_PORT_TUNE1 */

			 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */

			 0x210 /* QUSB2PHY_PWR_CTRL1 */

			 0x230 /* QUSB2PHY_INTR_CTRL */

			 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */

			 0x254 /* QUSB2PHY_TEST1 */

			 0x198 /* PLL_BIAS_CONTROL_2 */

			 0x27c /* QUSB2PHY_DEBUG_CTRL1 */

			 0x280 /* QUSB2PHY_DEBUG_CTRL2 */

			 0x2a0>; /* QUSB2PHY_STAT5 */



		qcom,qusb-phy-init-seq =

			/* <value reg_offset> */

			<0x23 0x210 /* PWR_CTRL1 */

			 0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

			 0x7c 0x18c /* PLL_CLOCK_INVERTERS */

			 0x80 0x2c  /* PLL_CMODE */

			 0x0a 0x184 /* PLL_LOCK_DELAY */

			 0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

			 0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			 0x22 0x198 /* PLL_BIAS_CONTROL_2 */

			 0x21 0x214 /* PWR_CTRL2 */

			 0x08 0x220 /* IMP_CTRL1 */

			 0x58 0x224 /* IMP_CTRL2 */

			 0x45 0x240 /* TUNE1 */

			 0x29 0x244 /* TUNE2 */

			 0xca 0x248 /* TUNE3 */

			 0x04 0x24c /* TUNE4 */

			 0x03 0x250 /* TUNE5 */

			 0x30 0x23c /* CHG_CTRL2 */

			 0x22 0x210>; /* PWR_CTRL1 */



		qcom,qusb-phy-host-init-seq =

			/* <value reg_offset> */

			<0x23 0x210 /* PWR_CTRL1 */

			0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

			0x7c 0x18c /* PLL_CLOCK_INVERTERS */

			0x80 0x2c  /* PLL_CMODE */

			0x0a 0x184 /* PLL_LOCK_DELAY */

			0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

			0x40 0x194 /* PLL_BIAS_CONTROL_1 */

			0x22 0x198 /* PLL_BIAS_CONTROL_2 */

			0x21 0x214 /* PWR_CTRL2 */

			0x08 0x220 /* IMP_CTRL1 */

			0x58 0x224 /* IMP_CTRL2 */

			0x45 0x240 /* TUNE1 */

			0x29 0x244 /* TUNE2 */

			0xca 0x248 /* TUNE3 */

			0x04 0x24c /* TUNE4 */

			0x03 0x250 /* TUNE5 */

			0x30 0x23c /* CHG_CTRL2 */

			0x22 0x210>; /* PWR_CTRL1 */



		phy_type= "utmi";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

		clock-names = "ref_clk_src", "cfg_ahb_clk";



		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

	};



	/* Primary USB port related QMP USB DP Combo PHY */

	usb_qmp_dp_phy: ssphy@88e8000 {

		compatible = "qcom,usb-ssphy-qmp-dp-combo";

		reg = <0x88e8000 0x3000>;

		reg-names = "qmp_phy_base";

		vdd-supply = <&pm6150_l4>;

		qcom,vdd-voltage-level = <0 880000 880000>;

		core-supply = <&pm6150l_l3>;

		qcom,vbus-valid-override;

		qcom,qmp-phy-init-seq =

			/* <reg_offset, value, delay> */

			<USB3_DP_QSERDES_COM_PLL_IVCO 0x07 0

			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x14 0

			USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0

			USB3_DP_QSERDES_COM_CLK_SELECT 0x30 0

			USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x02 0

			USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x08 0

			USB3_DP_QSERDES_COM_CMN_CONFIG 0x16 0

			USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0

			USB3_DP_QSERDES_COM_HSCLK_SEL 0x80 0

			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

			USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0

			USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x3f 0

			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x01 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0xc9 0

			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0  0x0a 0

			USB3_DP_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0

			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0

			USB3_DP_QSERDES_COM_CORE_CLK_EN 0x00 0

			USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x00 0

			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x00 0

			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

			USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0

			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0

			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0

			USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x00 0

			USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x00 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1 0x85 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2 0x07 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0

			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x03 0

			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0

			USB3_DP_QSERDES_RXA_RX_MODE_00 0x05 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0

			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

			USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x03 0

			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0

			USB3_DP_QSERDES_RXB_RX_MODE_00 0x05 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0

			USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x06 0

			USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x06 0

			USB3_DP_PCS_FLL_CNTRL2 0x83 0

			USB3_DP_PCS_FLL_CNT_VAL_L 0x09 0

			USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0xa2 0

			USB3_DP_PCS_FLL_MAN_CODE 0x40 0

			USB3_DP_PCS_FLL_CNTRL1 0x02 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd1 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1f 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x47 0

			USB3_DP_PCS_POWER_STATE_CONFIG2 0x1b 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xcc 0

			USB3_DP_PCS_TXMGN_V0 0x9f 0

			USB3_DP_PCS_TXMGN_V1 0x9f 0

			USB3_DP_PCS_TXMGN_V2 0xb7 0

			USB3_DP_PCS_TXMGN_V3 0x4e 0

			USB3_DP_PCS_TXMGN_V4 0x65 0

			USB3_DP_PCS_TXMGN_LS 0x6b 0

			USB3_DP_PCS_TXDEEMPH_M6DB_V0 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_V0 0x0d 0

			USB3_DP_PCS_TXDEEMPH_M6DB_V1 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_V1 0x0d 0

			USB3_DP_PCS_TXDEEMPH_M6DB_V2 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_V2 0x0d 0

			USB3_DP_PCS_TXDEEMPH_M6DB_V3 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_V3 0x1d 0

			USB3_DP_PCS_TXDEEMPH_M6DB_V4 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_V4 0x0d 0

			USB3_DP_PCS_TXDEEMPH_M6DB_LS 0x15 0

			USB3_DP_PCS_TXDEEMPH_M3P5DB_LS 0x0d 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x60 0

			USB3_DP_PCS_RATE_SLEW_CNTRL 0x02 0

			USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0

			USB3_DP_PCS_TSYNC_RSYNC_TIME 0x44 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

			USB3_DP_PCS_RCVR_DTCT_DLY_U3_L 0x40 0

			USB3_DP_PCS_RCVR_DTCT_DLY_U3_H 0x00 0

			USB3_DP_PCS_RXEQTRAINING_WAIT_TIME 0x75 0

			USB3_DP_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0

			USB3_DP_PCS_RXEQTRAINING_RUN_TIME 0x13 0

			USB3_DP_PCS_LFPS_DET_HIGH_COUNT_VAL 0x04 0

			0xffffffff 0xffffffff 0>;



		qcom,qmp-phy-reg-offset =

			<USB3_DP_PCS_PCS_STATUS

			USB3_DP_PCS_AUTONOMOUS_MODE_CTRL

			USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR

			USB3_DP_PCS_POWER_DOWN_CONTROL

			USB3_DP_PCS_SW_RESET

			USB3_DP_PCS_START_CONTROL

			USB3_DP_PCS_MISC_TYPEC_CTRL

			USB3_DP_PHY_DP_DP_PHY_PD_CTL

			USB3_DP_COM_POWER_DOWN_CTRL

			USB3_DP_COM_SW_RESET

			USB3_DP_COM_RESET_OVRD_CTRL

			USB3_DP_COM_PHY_MODE_CTRL

			USB3_DP_COM_TYPEC_CTRL

			USB3_DP_COM_SWI_CTRL

			USB3_DP_PCS_MISC_CLAMP_ENABLE>;



		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",

				"ref_clk", "com_aux_clk", "cfg_ahb_clk";



		resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,

			<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;

		reset-names = "global_phy_reset", "phy_reset";

	};



	usb_audio_qmi_dev {

		compatible = "qcom,usb-audio-qmi-dev";

		iommus = <&apps_smmu 0x1b2f 0x0>;

		qcom,usb-audio-stream-id = <0xf>;

		qcom,usb-audio-intr-num = <2>;

	};

};

arch/arm64/boot/dts/qcom/atoll.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -2166,6 +2166,14 @@ 
#include "atoll-usb.dtsi"

#include "atoll-vidc.dtsi"



&usb0 {

	extcon = <&pm6150_pdphy>, <&pm6150_charger>;

};



&usb_qmp_dp_phy {

	extcon = <&pm6150_pdphy>;

};



&pm6150_vadc {

	pinctrl-names = "default";

	pinctrl-0 = <&nvm_therm_default &sdm_skin_therm_default>;

include/dt-bindings/phy/qcom,atoll-qmp-usb3.h

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