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Commit ddcc9640 authored by Michael Adisumarta's avatar Michael Adisumarta Committed by Gerrit - the friendly Code Review server
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msm: ipa: Checksum validation changes



Change DL/UL WAN pipe configurations for CS offload.
Add new 8 bytes qmap header for DL CS offload.
Add a CS offload enum for QMAP_DL cS offload.

Change-Id: If23ed20a797db143da6dca61fa4c3080a347af1d
Signed-off-by: default avatarMichael Adisumarta <madisuma@codeaurora.org>
parent f43dabe3
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+3 −0
Original line number Diff line number Diff line
@@ -978,6 +978,9 @@ static void ipa_pkt_status_parse(
		else
			exception_type = IPAHAL_PKT_STATUS_EXCEPTION_NAT;
		break;
	case 229:
		exception_type = IPAHAL_PKT_STATUS_EXCEPTION_CSUM;
		break;
	default:
		IPAHAL_ERR("unsupported Status Exception type 0x%x\n",
			hw_status->exception);
+1 −0
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ enum ipahal_pkt_status_exception {
	 */
	IPAHAL_PKT_STATUS_EXCEPTION_NAT,
	IPAHAL_PKT_STATUS_EXCEPTION_IPV6CT,
	IPAHAL_PKT_STATUS_EXCEPTION_CSUM,
	IPAHAL_PKT_STATUS_EXCEPTION_MAX,
};

+32 −5
Original line number Diff line number Diff line
@@ -194,6 +194,22 @@ static int ipa3_setup_a7_qmap_hdr(void)

	strlcpy(hdr_entry->name, IPA_A7_QMAP_HDR_NAME,
				IPA_RESOURCE_NAME_MAX);
	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5) {
		hdr_entry->hdr_len = IPA_DL_CHECKSUM_LENGTH; /* 8 bytes */
		/* new DL QMAP header format */
		hdr->hdr[0].hdr[0] = 0x40;
		hdr->hdr[0].hdr[1] = 0;
		hdr->hdr[0].hdr[2] = 0;
		hdr->hdr[0].hdr[3] = 0;
		hdr->hdr[0].hdr[4] = 0x4;
		/*
		 * Need to set csum required/valid bit on which will be replaced
		 * by HW if checksum is incorrect after validation
		 */
		hdr->hdr[0].hdr[5] = 0x80;
		hdr->hdr[0].hdr[6] = 0;
		hdr->hdr[0].hdr[7] = 0;
	} else
		hdr_entry->hdr_len = IPA_QMAP_HEADER_LENGTH; /* 4 bytes */

	if (ipa3_add_hdr(hdr)) {
@@ -1302,9 +1318,15 @@ static int handle3_ingress_format(struct net_device *dev,
	}

	ipa_wan_ep_cfg = &rmnet_ipa3_ctx->ipa_to_apps_ep_cfg;
	if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM)
	if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) {
		if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)
			ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en =
				IPA_ENABLE_CS_DL_QMAP;
		else
			ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en =
				IPA_ENABLE_CS_OFFLOAD_DL;
		IPAWANDBG("DL chksum set\n");
	}

	if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) {
		IPAWANDBG("get AGG size %d count %d\n",
@@ -1323,6 +1345,10 @@ static int handle3_ingress_format(struct net_device *dev,
		}
	}

	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 &&
		(in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM)
		ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8;
	else
		ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4;
	ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1;
	ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 1;
@@ -1389,6 +1415,7 @@ static int handle3_egress_format(struct net_device *dev,

	ipa_wan_ep_cfg = &rmnet_ipa3_ctx->apps_to_ipa_ep_cfg;
	if ((e->u.data) & RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM) {
		IPAWANDBG("UL chksum set\n");
		ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 8;
		ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en =
			IPA_ENABLE_CS_OFFLOAD_UL;
+7 −0
Original line number Diff line number Diff line
@@ -373,7 +373,14 @@ struct ipa_ep_cfg_deaggr {
 */
enum ipa_cs_offload {
	IPA_DISABLE_CS_OFFLOAD,
	/*
	 * For enum value = 1, we check the csum required/valid bit which is the
	 * same bit used for both DL and UL but have different meanings.
	 * For UL pipe, HW checks if it needs to perform Csum caluclation.
	 * For DL pipe, HW checks if the csum is valid or invalid
	 */
	IPA_ENABLE_CS_OFFLOAD_UL,
	IPA_ENABLE_CS_DL_QMAP = IPA_ENABLE_CS_OFFLOAD_UL,
	IPA_ENABLE_CS_OFFLOAD_DL,
	IPA_CS_RSVD
};