Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dd7bd109 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools: Copy the header files needed by perf tools 

Those kernel files were being directly accessed, which we're not
allowing anymore to avoid that changes in the kernel side break tooling.

Warn if these copies drift from the original files.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Yarygin <yarygin@linux.vnet.ibm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: David Ahern <dsahern@gmail.com>
Cc: Eric Auger <eric.auger@linaro.org>
Cc: Hemant Kumar <hemant@linux.vnet.ibm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Wang Nan <wangnan0@huawei.com>
Cc: Yunlong Song <yunlong.song@huawei.com>
Link: http://lkml.kernel.org/n/tip-mnopguymhnwzjhw3mowllvsy@git.kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent f2d3adf4

tools/arch/arm/include/uapi/asm/kvm.h

0 → 100644
+224 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2012 - Virtual Open Systems and Columbia University

 * Author: Christoffer Dall <c.dall@virtualopensystems.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

 */



#ifndef __ARM_KVM_H__

#define __ARM_KVM_H__



#include <linux/types.h>

#include <linux/psci.h>

#include <asm/ptrace.h>



#define __KVM_HAVE_GUEST_DEBUG

#define __KVM_HAVE_IRQ_LINE

#define __KVM_HAVE_READONLY_MEM



#define KVM_REG_SIZE(id)						\

	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))



/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */

#define KVM_ARM_SVC_sp		svc_regs[0]

#define KVM_ARM_SVC_lr		svc_regs[1]

#define KVM_ARM_SVC_spsr	svc_regs[2]

#define KVM_ARM_ABT_sp		abt_regs[0]

#define KVM_ARM_ABT_lr		abt_regs[1]

#define KVM_ARM_ABT_spsr	abt_regs[2]

#define KVM_ARM_UND_sp		und_regs[0]

#define KVM_ARM_UND_lr		und_regs[1]

#define KVM_ARM_UND_spsr	und_regs[2]

#define KVM_ARM_IRQ_sp		irq_regs[0]

#define KVM_ARM_IRQ_lr		irq_regs[1]

#define KVM_ARM_IRQ_spsr	irq_regs[2]



/* Valid only for fiq_regs in struct kvm_regs */

#define KVM_ARM_FIQ_r8		fiq_regs[0]

#define KVM_ARM_FIQ_r9		fiq_regs[1]

#define KVM_ARM_FIQ_r10		fiq_regs[2]

#define KVM_ARM_FIQ_fp		fiq_regs[3]

#define KVM_ARM_FIQ_ip		fiq_regs[4]

#define KVM_ARM_FIQ_sp		fiq_regs[5]

#define KVM_ARM_FIQ_lr		fiq_regs[6]

#define KVM_ARM_FIQ_spsr	fiq_regs[7]



struct kvm_regs {

	struct pt_regs usr_regs;	/* R0_usr - R14_usr, PC, CPSR */

	unsigned long svc_regs[3];	/* SP_svc, LR_svc, SPSR_svc */

	unsigned long abt_regs[3];	/* SP_abt, LR_abt, SPSR_abt */

	unsigned long und_regs[3];	/* SP_und, LR_und, SPSR_und */

	unsigned long irq_regs[3];	/* SP_irq, LR_irq, SPSR_irq */

	unsigned long fiq_regs[8];	/* R8_fiq - R14_fiq, SPSR_fiq */

};



/* Supported Processor Types */

#define KVM_ARM_TARGET_CORTEX_A15	0

#define KVM_ARM_TARGET_CORTEX_A7	1

#define KVM_ARM_NUM_TARGETS		2



/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */

#define KVM_ARM_DEVICE_TYPE_SHIFT	0

#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)

#define KVM_ARM_DEVICE_ID_SHIFT		16

#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)



/* Supported device IDs */

#define KVM_ARM_DEVICE_VGIC_V2		0



/* Supported VGIC address types  */

#define KVM_VGIC_V2_ADDR_TYPE_DIST	0

#define KVM_VGIC_V2_ADDR_TYPE_CPU	1



#define KVM_VGIC_V2_DIST_SIZE		0x1000

#define KVM_VGIC_V2_CPU_SIZE		0x2000



#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */

#define KVM_ARM_VCPU_PSCI_0_2		1 /* CPU uses PSCI v0.2 */



struct kvm_vcpu_init {

	__u32 target;

	__u32 features[7];

};



struct kvm_sregs {

};



struct kvm_fpu {

};



struct kvm_guest_debug_arch {

};



struct kvm_debug_exit_arch {

};



struct kvm_sync_regs {

};



struct kvm_arch_memory_slot {

};



/* If you need to interpret the index values, here is the key: */

#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000

#define KVM_REG_ARM_COPROC_SHIFT	16

#define KVM_REG_ARM_32_OPC2_MASK	0x0000000000000007

#define KVM_REG_ARM_32_OPC2_SHIFT	0

#define KVM_REG_ARM_OPC1_MASK		0x0000000000000078

#define KVM_REG_ARM_OPC1_SHIFT		3

#define KVM_REG_ARM_CRM_MASK		0x0000000000000780

#define KVM_REG_ARM_CRM_SHIFT		7

#define KVM_REG_ARM_32_CRN_MASK		0x0000000000007800

#define KVM_REG_ARM_32_CRN_SHIFT	11



#define ARM_CP15_REG_SHIFT_MASK(x,n) \

	(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)



#define __ARM_CP15_REG(op1,crn,crm,op2) \

	(KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \

	ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \

	ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \

	ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \

	ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))



#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)



#define __ARM_CP15_REG64(op1,crm) \

	(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)

#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)



#define KVM_REG_ARM_TIMER_CTL		ARM_CP15_REG32(0, 14, 3, 1)

#define KVM_REG_ARM_TIMER_CNT		ARM_CP15_REG64(1, 14)

#define KVM_REG_ARM_TIMER_CVAL		ARM_CP15_REG64(3, 14)



/* Normal registers are mapped as coprocessor 16. */

#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / 4)



/* Some registers need more space to represent values. */

#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00

#define KVM_REG_ARM_DEMUX_ID_SHIFT	8

#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)

#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF

#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0



/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */

#define KVM_REG_ARM_VFP			(0x0012 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_VFP_MASK		0x000000000000FFFF

#define KVM_REG_ARM_VFP_BASE_REG	0x0

#define KVM_REG_ARM_VFP_FPSID		0x1000

#define KVM_REG_ARM_VFP_FPSCR		0x1001

#define KVM_REG_ARM_VFP_MVFR1		0x1006

#define KVM_REG_ARM_VFP_MVFR0		0x1007

#define KVM_REG_ARM_VFP_FPEXC		0x1008

#define KVM_REG_ARM_VFP_FPINST		0x1009

#define KVM_REG_ARM_VFP_FPINST2		0x100A



/* Device Control API: ARM VGIC */

#define KVM_DEV_ARM_VGIC_GRP_ADDR	0

#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1

#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2

#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32

#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)

#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0

#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)

#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3

#define KVM_DEV_ARM_VGIC_GRP_CTRL       4

#define   KVM_DEV_ARM_VGIC_CTRL_INIT    0



/* KVM_IRQ_LINE irq field index values */

#define KVM_ARM_IRQ_TYPE_SHIFT		24

#define KVM_ARM_IRQ_TYPE_MASK		0xff

#define KVM_ARM_IRQ_VCPU_SHIFT		16

#define KVM_ARM_IRQ_VCPU_MASK		0xff

#define KVM_ARM_IRQ_NUM_SHIFT		0

#define KVM_ARM_IRQ_NUM_MASK		0xffff



/* irq_type field */

#define KVM_ARM_IRQ_TYPE_CPU		0

#define KVM_ARM_IRQ_TYPE_SPI		1

#define KVM_ARM_IRQ_TYPE_PPI		2



/* out-of-kernel GIC cpu interrupt injection irq_number field */

#define KVM_ARM_IRQ_CPU_IRQ		0

#define KVM_ARM_IRQ_CPU_FIQ		1



/*

 * This used to hold the highest supported SPI, but it is now obsolete

 * and only here to provide source code level compatibility with older

 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.

 */

#ifndef __KERNEL__

#define KVM_ARM_IRQ_GIC_MAX		127

#endif



/* One single KVM irqchip, ie. the VGIC */

#define KVM_NR_IRQCHIPS          1



/* PSCI interface */

#define KVM_PSCI_FN_BASE		0x95c1ba5e

#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))



#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)

#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)

#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)

#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)



#define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS

#define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED

#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS

#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED



#endif /* __ARM_KVM_H__ */

tools/arch/arm64/include/uapi/asm/kvm.h

0 → 100644
+258 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2012,2013 - ARM Ltd

 * Author: Marc Zyngier <marc.zyngier@arm.com>

 *

 * Derived from arch/arm/include/uapi/asm/kvm.h:

 * Copyright (C) 2012 - Virtual Open Systems and Columbia University

 * Author: Christoffer Dall <c.dall@virtualopensystems.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __ARM_KVM_H__

#define __ARM_KVM_H__



#define KVM_SPSR_EL1	0

#define KVM_SPSR_SVC	KVM_SPSR_EL1

#define KVM_SPSR_ABT	1

#define KVM_SPSR_UND	2

#define KVM_SPSR_IRQ	3

#define KVM_SPSR_FIQ	4

#define KVM_NR_SPSR	5



#ifndef __ASSEMBLY__

#include <linux/psci.h>

#include <linux/types.h>

#include <asm/ptrace.h>



#define __KVM_HAVE_GUEST_DEBUG

#define __KVM_HAVE_IRQ_LINE

#define __KVM_HAVE_READONLY_MEM



#define KVM_REG_SIZE(id)						\

	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))



struct kvm_regs {

	struct user_pt_regs regs;	/* sp = sp_el0 */



	__u64	sp_el1;

	__u64	elr_el1;



	__u64	spsr[KVM_NR_SPSR];



	struct user_fpsimd_state fp_regs;

};



/*

 * Supported CPU Targets - Adding a new target type is not recommended,

 * unless there are some special registers not supported by the

 * genericv8 syreg table.

 */

#define KVM_ARM_TARGET_AEM_V8		0

#define KVM_ARM_TARGET_FOUNDATION_V8	1

#define KVM_ARM_TARGET_CORTEX_A57	2

#define KVM_ARM_TARGET_XGENE_POTENZA	3

#define KVM_ARM_TARGET_CORTEX_A53	4

/* Generic ARM v8 target */

#define KVM_ARM_TARGET_GENERIC_V8	5



#define KVM_ARM_NUM_TARGETS		6



/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */

#define KVM_ARM_DEVICE_TYPE_SHIFT	0

#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)

#define KVM_ARM_DEVICE_ID_SHIFT		16

#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)



/* Supported device IDs */

#define KVM_ARM_DEVICE_VGIC_V2		0



/* Supported VGIC address types  */

#define KVM_VGIC_V2_ADDR_TYPE_DIST	0

#define KVM_VGIC_V2_ADDR_TYPE_CPU	1



#define KVM_VGIC_V2_DIST_SIZE		0x1000

#define KVM_VGIC_V2_CPU_SIZE		0x2000



/* Supported VGICv3 address types  */

#define KVM_VGIC_V3_ADDR_TYPE_DIST	2

#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3



#define KVM_VGIC_V3_DIST_SIZE		SZ_64K

#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)



#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */

#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */

#define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */

#define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */



struct kvm_vcpu_init {

	__u32 target;

	__u32 features[7];

};



struct kvm_sregs {

};



struct kvm_fpu {

};



/*

 * See v8 ARM ARM D7.3: Debug Registers

 *

 * The architectural limit is 16 debug registers of each type although

 * in practice there are usually less (see ID_AA64DFR0_EL1).

 *

 * Although the control registers are architecturally defined as 32

 * bits wide we use a 64 bit structure here to keep parity with

 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as

 * 64 bit values. It also allows for the possibility of the

 * architecture expanding the control registers without having to

 * change the userspace ABI.

 */

#define KVM_ARM_MAX_DBG_REGS 16

struct kvm_guest_debug_arch {

	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];

	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];

	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];

	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];

};



struct kvm_debug_exit_arch {

	__u32 hsr;

	__u64 far;	/* used for watchpoints */

};



/*

 * Architecture specific defines for kvm_guest_debug->control

 */



#define KVM_GUESTDBG_USE_SW_BP		(1 << 16)

#define KVM_GUESTDBG_USE_HW		(1 << 17)



struct kvm_sync_regs {

};



struct kvm_arch_memory_slot {

};



/* If you need to interpret the index values, here is the key: */

#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000

#define KVM_REG_ARM_COPROC_SHIFT	16



/* Normal registers are mapped as coprocessor 16. */

#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))



/* Some registers need more space to represent values. */

#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00

#define KVM_REG_ARM_DEMUX_ID_SHIFT	8

#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)

#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF

#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0



/* AArch64 system registers */

#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)

#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000

#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14

#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800

#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11

#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780

#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7

#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078

#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3

#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007

#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0



#define ARM64_SYS_REG_SHIFT_MASK(x,n) \

	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \

	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)



#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \

	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \

	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \

	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \

	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \

	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \

	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))



#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)



#define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)

#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)

#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)



/* Device Control API: ARM VGIC */

#define KVM_DEV_ARM_VGIC_GRP_ADDR	0

#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1

#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2

#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32

#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)

#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0

#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)

#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3

#define KVM_DEV_ARM_VGIC_GRP_CTRL	4

#define   KVM_DEV_ARM_VGIC_CTRL_INIT	0



/* Device Control API on vcpu fd */

#define KVM_ARM_VCPU_PMU_V3_CTRL	0

#define   KVM_ARM_VCPU_PMU_V3_IRQ	0

#define   KVM_ARM_VCPU_PMU_V3_INIT	1



/* KVM_IRQ_LINE irq field index values */

#define KVM_ARM_IRQ_TYPE_SHIFT		24

#define KVM_ARM_IRQ_TYPE_MASK		0xff

#define KVM_ARM_IRQ_VCPU_SHIFT		16

#define KVM_ARM_IRQ_VCPU_MASK		0xff

#define KVM_ARM_IRQ_NUM_SHIFT		0

#define KVM_ARM_IRQ_NUM_MASK		0xffff



/* irq_type field */

#define KVM_ARM_IRQ_TYPE_CPU		0

#define KVM_ARM_IRQ_TYPE_SPI		1

#define KVM_ARM_IRQ_TYPE_PPI		2



/* out-of-kernel GIC cpu interrupt injection irq_number field */

#define KVM_ARM_IRQ_CPU_IRQ		0

#define KVM_ARM_IRQ_CPU_FIQ		1



/*

 * This used to hold the highest supported SPI, but it is now obsolete

 * and only here to provide source code level compatibility with older

 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.

 */

#ifndef __KERNEL__

#define KVM_ARM_IRQ_GIC_MAX		127

#endif



/* One single KVM irqchip, ie. the VGIC */

#define KVM_NR_IRQCHIPS          1



/* PSCI interface */

#define KVM_PSCI_FN_BASE		0x95c1ba5e

#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))



#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)

#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)

#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)

#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)



#define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS

#define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED

#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS

#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED



#endif



#endif /* __ARM_KVM_H__ */

tools/arch/mips/include/uapi/asm/kvm.h

0 → 100644
+208 −0
Original line number Original line Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.

 * Copyright (C) 2013 Cavium, Inc.

 * Authors: Sanjay Lal <sanjayl@kymasys.com>

 */



#ifndef __LINUX_KVM_MIPS_H

#define __LINUX_KVM_MIPS_H



#include <linux/types.h>



/*

 * KVM MIPS specific structures and definitions.

 *

 * Some parts derived from the x86 version of this file.

 */



/*

 * for KVM_GET_REGS and KVM_SET_REGS

 *

 * If Config[AT] is zero (32-bit CPU), the register contents are

 * stored in the lower 32-bits of the struct kvm_regs fields and sign

 * extended to 64-bits.

 */

struct kvm_regs {

	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */

	__u64 gpr[32];

	__u64 hi;

	__u64 lo;

	__u64 pc;

};



/*

 * for KVM_GET_FPU and KVM_SET_FPU

 */

struct kvm_fpu {

};





/*

 * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various

 * registers.  The id field is broken down as follows:

 *

 *  bits[63..52] - As per linux/kvm.h

 *  bits[51..32] - Must be zero.

 *  bits[31..16] - Register set.

 *

 * Register set = 0: GP registers from kvm_regs (see definitions below).

 *

 * Register set = 1: CP0 registers.

 *  bits[15..8]  - Must be zero.

 *  bits[7..3]   - Register 'rd'  index.

 *  bits[2..0]   - Register 'sel' index.

 *

 * Register set = 2: KVM specific registers (see definitions below).

 *

 * Register set = 3: FPU / MSA registers (see definitions below).

 *

 * Other sets registers may be added in the future.  Each set would

 * have its own identifier in bits[31..16].

 */



#define KVM_REG_MIPS_GP		(KVM_REG_MIPS | 0x0000000000000000ULL)

#define KVM_REG_MIPS_CP0	(KVM_REG_MIPS | 0x0000000000010000ULL)

#define KVM_REG_MIPS_KVM	(KVM_REG_MIPS | 0x0000000000020000ULL)

#define KVM_REG_MIPS_FPU	(KVM_REG_MIPS | 0x0000000000030000ULL)





/*

 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.

 */



#define KVM_REG_MIPS_R0		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  0)

#define KVM_REG_MIPS_R1		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  1)

#define KVM_REG_MIPS_R2		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  2)

#define KVM_REG_MIPS_R3		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  3)

#define KVM_REG_MIPS_R4		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  4)

#define KVM_REG_MIPS_R5		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  5)

#define KVM_REG_MIPS_R6		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  6)

#define KVM_REG_MIPS_R7		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  7)

#define KVM_REG_MIPS_R8		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  8)

#define KVM_REG_MIPS_R9		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  9)

#define KVM_REG_MIPS_R10	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)

#define KVM_REG_MIPS_R11	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)

#define KVM_REG_MIPS_R12	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)

#define KVM_REG_MIPS_R13	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)

#define KVM_REG_MIPS_R14	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)

#define KVM_REG_MIPS_R15	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)

#define KVM_REG_MIPS_R16	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)

#define KVM_REG_MIPS_R17	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)

#define KVM_REG_MIPS_R18	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)

#define KVM_REG_MIPS_R19	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)

#define KVM_REG_MIPS_R20	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)

#define KVM_REG_MIPS_R21	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)

#define KVM_REG_MIPS_R22	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)

#define KVM_REG_MIPS_R23	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)

#define KVM_REG_MIPS_R24	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)

#define KVM_REG_MIPS_R25	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)

#define KVM_REG_MIPS_R26	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)

#define KVM_REG_MIPS_R27	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)

#define KVM_REG_MIPS_R28	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)

#define KVM_REG_MIPS_R29	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)

#define KVM_REG_MIPS_R30	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)

#define KVM_REG_MIPS_R31	(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)



#define KVM_REG_MIPS_HI		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)

#define KVM_REG_MIPS_LO		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)

#define KVM_REG_MIPS_PC		(KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)





/*

 * KVM_REG_MIPS_KVM - KVM specific control registers.

 */



/*

 * CP0_Count control

 * DC:    Set 0: Master disable CP0_Count and set COUNT_RESUME to now

 *        Set 1: Master re-enable CP0_Count with unchanged bias, handling timer

 *               interrupts since COUNT_RESUME

 *        This can be used to freeze the timer to get a consistent snapshot of

 *        the CP0_Count and timer interrupt pending state, while also resuming

 *        safely without losing time or guest timer interrupts.

 * Other: Reserved, do not change.

 */

#define KVM_REG_MIPS_COUNT_CTL	    (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)

#define KVM_REG_MIPS_COUNT_CTL_DC	0x00000001



/*

 * CP0_Count resume monotonic nanoseconds

 * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master

 * disable). Any reads and writes of Count related registers while

 * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is

 * cleared again (master enable) any timer interrupts since this time will be

 * emulated.

 * Modifications to times in the future are rejected.

 */

#define KVM_REG_MIPS_COUNT_RESUME   (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)

/*

 * CP0_Count rate in Hz

 * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without

 * discontinuities in CP0_Count.

 */

#define KVM_REG_MIPS_COUNT_HZ	    (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)





/*

 * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.

 *

 *  bits[15..8]  - Register subset (see definitions below).

 *  bits[7..5]   - Must be zero.

 *  bits[4..0]   - Register number within register subset.

 */



#define KVM_REG_MIPS_FPR	(KVM_REG_MIPS_FPU | 0x0000000000000000ULL)

#define KVM_REG_MIPS_FCR	(KVM_REG_MIPS_FPU | 0x0000000000000100ULL)

#define KVM_REG_MIPS_MSACR	(KVM_REG_MIPS_FPU | 0x0000000000000200ULL)



/*

 * KVM_REG_MIPS_FPR - Floating point / Vector registers.

 */

#define KVM_REG_MIPS_FPR_32(n)	(KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32  | (n))

#define KVM_REG_MIPS_FPR_64(n)	(KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64  | (n))

#define KVM_REG_MIPS_VEC_128(n)	(KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))



/*

 * KVM_REG_MIPS_FCR - Floating point control registers.

 */

#define KVM_REG_MIPS_FCR_IR	(KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 |  0)

#define KVM_REG_MIPS_FCR_CSR	(KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)



/*

 * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.

 */

#define KVM_REG_MIPS_MSA_IR	 (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  0)

#define KVM_REG_MIPS_MSA_CSR	 (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  1)





/*

 * KVM MIPS specific structures and definitions

 *

 */

struct kvm_debug_exit_arch {

	__u64 epc;

};



/* for KVM_SET_GUEST_DEBUG */

struct kvm_guest_debug_arch {

};



/* definition of registers in kvm_run */

struct kvm_sync_regs {

};



/* dummy definition */

struct kvm_sregs {

};



struct kvm_mips_interrupt {

	/* in */

	__u32 cpu;

	__u32 irq;

};



#endif /* __LINUX_KVM_MIPS_H */