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Commit dcd87885 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: disable/enable link LPM during bandwidth scaling 



When switching link width or gen speed, the link needs to be in
L0. Disable all link lower power modes to keep it in L0 until
the switch completes.

Change-Id: Ifbfb6880eee3dc3345bf1cbbb39dffd0ca89e648
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 61841ca3

drivers/pci/host/pci-msm.c

+12 −9
Original line number Diff line number Diff line
@@ -6135,9 +6135,6 @@ static int msm_pcie_link_retrain(struct msm_pcie_dev_t *pcie_dev, 
	u32 cnt_max = 1000; /* 100ms timeout */

	u32 link_status_lbms_mask = PCI_EXP_LNKSTA_LBMS << PCI_EXP_LNKCTL;



	/* force link to L0 */

	msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL,  0, BIT(5));



	cnt = 0;

	/* confirm link is in L0 */

	while (((readl_relaxed(pcie_dev->parf + PCIE20_PARF_LTSSM) &
@@ -6170,9 +6167,6 @@ static int msm_pcie_link_retrain(struct msm_pcie_dev_t *pcie_dev, 
		usleep_range(100, 105);

	}



	/* re-enable link LPM */

	msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);



	return 0;

}
@@ -6249,12 +6243,16 @@ int msm_pcie_set_link_bandwidth(struct pci_dev *pci_dev, u16 target_link_speed, 
						PCI_EXP_LNKSTA_CLS,

						target_link_speed);



	/* disable link L1. Need to be in L0 for gen switch */

	msm_pcie_config_l1(pcie_dev, root_pci_dev, false);

	msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL,  0, BIT(5));



	if (target_link_speed > current_link_speed)

		msm_pcie_scale_link_bandwidth(pcie_dev, target_link_speed);



	ret = msm_pcie_link_retrain(pcie_dev, root_pci_dev);

	if (ret)

		return ret;

		goto out;



	pcie_capability_read_word(root_pci_dev, PCI_EXP_LNKSTA, &link_status);

	if ((link_status & PCI_EXP_LNKSTA_CLS) != target_link_speed ||
@@ -6263,13 +6261,18 @@ int msm_pcie_set_link_bandwidth(struct pci_dev *pci_dev, u16 target_link_speed, 
			"PCIe: RC%d: failed to switch bandwidth: target speed: %d width: %d\n",

			pcie_dev->rc_idx, target_link_speed,

			target_link_width >> PCI_EXP_LNKSTA_NLW_SHIFT);

		return -EIO;

		ret = -EIO;

		goto out;

	}



	if (target_link_speed < current_link_speed)

		msm_pcie_scale_link_bandwidth(pcie_dev, target_link_speed);

out:

	/* re-enable link L1 */

	msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);

	msm_pcie_config_l1(pcie_dev, root_pci_dev, true);



	return 0;

	return ret;

}

EXPORT_SYMBOL(msm_pcie_set_link_bandwidth);