Loading arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi +8 −5 Original line number Diff line number Diff line Loading @@ -41,16 +41,19 @@ }; &soc { clock_virt: qcom,virt-gcc { compatible = "qcom,virt-clk-sm6150-gcc"; clock_virt: qcom,virtio-gcc { compatible = "virtio,mmio"; reg = <0x1c200000 0x1000>; interrupts = <0 48 0>; #clock-cells = <1>; #reset-cells = <1>; }; clock_virt_scc: qcom,virt-scc { compatible = "qcom,virt-clk-sm6150-scc"; clock_virt_scc: qcom,virtio-scc { compatible = "virtio,mmio"; reg = <0x1c300000 0x1000>; interrupts = <0 49 0>; #clock-cells = <1>; #reset-cells = <1>; }; regulator_virt: virtio_regulator@1c700000 { Loading Loading
arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi +8 −5 Original line number Diff line number Diff line Loading @@ -41,16 +41,19 @@ }; &soc { clock_virt: qcom,virt-gcc { compatible = "qcom,virt-clk-sm6150-gcc"; clock_virt: qcom,virtio-gcc { compatible = "virtio,mmio"; reg = <0x1c200000 0x1000>; interrupts = <0 48 0>; #clock-cells = <1>; #reset-cells = <1>; }; clock_virt_scc: qcom,virt-scc { compatible = "qcom,virt-clk-sm6150-scc"; clock_virt_scc: qcom,virtio-scc { compatible = "virtio,mmio"; reg = <0x1c300000 0x1000>; interrupts = <0 49 0>; #clock-cells = <1>; #reset-cells = <1>; }; regulator_virt: virtio_regulator@1c700000 { Loading