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Commit dc54c23b authored by Stephen Warren's avatar Stephen Warren Committed by Colin Cross
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ARM: Tegra: Make tegra_dma_init a postcore_initcall 



The following commit makes the Tegra APB DMA engine fail to initialize
correctly: 0cf6230a
ARM: tegra: Move tegra_common_init to tegra_init_early

The reason is that tegra_init_early_ calls tegra_dma_init which calls
request_threaded_irq, which fails since the IRQ hasn't yet been marked
valid; that only happens in tegra_init_irq, which gets called after
tegra_init_early.

This used to work OK, since tegra_init_early was tegra_common_init, which
got called after tegra_init_irq, basically from the beginning of
tegra_harmony_init.

Solve this by converting tegra_dma_init to a postcore_initcall. This makes
it execute late enough that IRQs are marked valid, and avoids having to
add it back to every machine's init function.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarColin Cross <ccross@android.com>
parent 48e5114d

arch/arm/mach-tegra/common.c

+0 −4
Original line number Original line Diff line number Diff line
@@ -25,7 +25,6 @@ 
#include <asm/hardware/cache-l2x0.h>

#include <asm/hardware/cache-l2x0.h>





#include <mach/iomap.h>

#include <mach/iomap.h>

#include <mach/dma.h>

#include <mach/system.h>

#include <mach/system.h>





#include "board.h"

#include "board.h"
@@ -81,7 +80,4 @@ void __init tegra_init_early(void) 
	tegra_init_clock();

	tegra_init_clock();

	tegra_clk_init_from_table(common_clk_init_table);

	tegra_clk_init_from_table(common_clk_init_table);

	tegra_init_cache();

	tegra_init_cache();

#ifdef CONFIG_TEGRA_SYSTEM_DMA

	tegra_dma_init();

#endif

}
 
}

arch/arm/mach-tegra/dma.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -743,6 +743,7 @@ int __init tegra_dma_init(void) 
	}

	}

	return ret;

	return ret;

}

}

postcore_initcall(tegra_dma_init);





#ifdef CONFIG_PM

#ifdef CONFIG_PM

static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];

static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];