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Commit dbcc7e63 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: enable two LMH DCVS instances for TRINKET"

parents 96bb78be 889e40b7

arch/arm64/boot/dts/qcom/trinket-thermal.dtsi

+11 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
&clock_cpucc {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@0xf550800 {

	lmh_dcvs0: qcom,limits-dcvs@f521000 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;
@@ -25,6 +25,16 @@ 
		qcom,plat-mitigation-disable;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@f523000 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0xf550800 0x1000>,

			<0xf523000 0x1000>;

		qcom,plat-mitigation-disable;

		#thermal-sensor-cells = <0>;

	};

};



&soc {

arch/arm64/boot/dts/qcom/trinket.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -175,7 +175,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -208,7 +208,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;



			L1_I_101: l1-icache {
@@ -236,7 +236,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;



			L1_I_102: l1-icache {
@@ -264,7 +264,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			#cooling-cells = <2>;



			L1_I_103: l1-icache {