Loading drivers/power/supply/qcom/qpnp-smb5.c +8 −0 Original line number Diff line number Diff line Loading @@ -1982,6 +1982,14 @@ static int smb5_init_hw(struct smb5 *chip) return rc; } rc = smblib_write(chg, CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG, FAST_CHARGE_SAFETY_TIMER_768_MIN); if (rc < 0) { dev_err(chg->dev, "Couldn't set CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG rc=%d\n", rc); return rc; } rc = smblib_masked_write(chg, CHGR_CFG2_REG, RECHG_MASK, (chip->dt.auto_recharge_vbat_mv != -EINVAL) ? VBAT_BASED_RECHG_BIT : 0); Loading drivers/power/supply/qcom/smb5-reg.h +6 −0 Original line number Diff line number Diff line Loading @@ -108,6 +108,12 @@ enum { #define CHGR_JEITA_THRESHOLD_BASE_REG(i) (CHGR_BASE + 0x94 + (i * 4)) #define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG (CHGR_BASE + 0xA2) #define FAST_CHARGE_SAFETY_TIMER_192_MIN 0x0 #define FAST_CHARGE_SAFETY_TIMER_384_MIN 0x1 #define FAST_CHARGE_SAFETY_TIMER_768_MIN 0x2 #define FAST_CHARGE_SAFETY_TIMER_1536_MIN 0x3 #define CHGR_ENG_CHARGING_CFG_REG (CHGR_BASE + 0xC0) #define CHGR_ITERM_USE_ANALOG_BIT BIT(3) Loading Loading
drivers/power/supply/qcom/qpnp-smb5.c +8 −0 Original line number Diff line number Diff line Loading @@ -1982,6 +1982,14 @@ static int smb5_init_hw(struct smb5 *chip) return rc; } rc = smblib_write(chg, CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG, FAST_CHARGE_SAFETY_TIMER_768_MIN); if (rc < 0) { dev_err(chg->dev, "Couldn't set CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG rc=%d\n", rc); return rc; } rc = smblib_masked_write(chg, CHGR_CFG2_REG, RECHG_MASK, (chip->dt.auto_recharge_vbat_mv != -EINVAL) ? VBAT_BASED_RECHG_BIT : 0); Loading
drivers/power/supply/qcom/smb5-reg.h +6 −0 Original line number Diff line number Diff line Loading @@ -108,6 +108,12 @@ enum { #define CHGR_JEITA_THRESHOLD_BASE_REG(i) (CHGR_BASE + 0x94 + (i * 4)) #define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG (CHGR_BASE + 0xA2) #define FAST_CHARGE_SAFETY_TIMER_192_MIN 0x0 #define FAST_CHARGE_SAFETY_TIMER_384_MIN 0x1 #define FAST_CHARGE_SAFETY_TIMER_768_MIN 0x2 #define FAST_CHARGE_SAFETY_TIMER_1536_MIN 0x3 #define CHGR_ENG_CHARGING_CFG_REG (CHGR_BASE + 0xC0) #define CHGR_ITERM_USE_ANALOG_BIT BIT(3) Loading