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Commit db669c11 authored by Ajay Agarwal's avatar Ajay Agarwal
Browse files

ARM: dts: msm: Fix pinctrl configuration for HS UART on sdmshrike 



Add 'active' pinctrl configuration for SE13 4 wire UART
definition so as to use proper biasing for the CTS and Rx GPIOs.
While at this, also modify the 'compatible' string definitions
for UART nodes to align with internal drivers.

Change-Id: I062e462ad3a368238c8b8ae8d1182e45ff872348
Signed-off-by: default avatarAjay Agarwal <ajaya@codeaurora.org>
parent 29444f60

arch/arm64/boot/dts/qcom/sdmshrike-qupv3.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -359,7 +359,7 @@ 


	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se12_2uart: qcom,qup_uart@a90000 {

		compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart";

		compatible = "qcom,msm-geni-console";

		reg = <0xa90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";
@@ -376,7 +376,7 @@ 


	/* Debug UART Instance for RUMI platform */

	qupv3_se10_2uart: qcom,qup_uart@a88000 {

		compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart";

		compatible = "qcom,msm-geni-console";

		reg = <0xa88000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";
@@ -625,14 +625,14 @@ 


	/* 4-wire UART */

	qupv3_se13_4uart: qcom,qup_uart@c8c000 {

		compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart";

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xc8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,

				<&qupv3_se13_default_tx>;

		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,