Merge "clk: qcom: gcc: Remove MSS clocks for SDMMAGPIE" (da919df9) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/gcc-sdmmagpie.c

+0 −110

Original line number	Diff line number	Diff line
		@@ -1698,109 +1698,6 @@ static struct clk_branch gcc_gpu_vs_clk = {
		},
		};

		static struct clk_branch gcc_mss_axis2_clk = {
		.halt_reg = 0x8a008,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8a008,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_axis2_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_cfg_ahb_clk = {
		.halt_reg = 0x8a000,
		.halt_check = BRANCH_HALT,
		.hwcg_reg = 0x8a000,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x8a000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_cfg_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_gpll0_div_clk_src = {
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(17),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_gpll0_div_clk_src",
		.parent_names = (const char *[]){
		"gcc_pll0_main_div_cdiv",
		},
		.num_parents = 1,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_mfab_axis_clk = {
		.halt_reg = 0x8a004,
		.halt_check = BRANCH_VOTED,
		.hwcg_reg = 0x8a004,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x8a004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_mfab_axis_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
		.halt_reg = 0x8a154,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x8a154,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_q6_memnoc_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_snoc_axi_clk = {
		.halt_reg = 0x8a150,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8a150,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_snoc_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_vs_clk = {
		.halt_reg = 0x7a048,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7a048,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_vs_clk",
		.parent_names = (const char *[]){
		"gcc_vsensor_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_npu_axi_clk = {
		.halt_reg = 0x4d008,
		.halt_check = BRANCH_HALT,
		@@ -3195,13 +3092,6 @@ static struct clk_regmap *gcc_sdmmagpie_clocks[] = {
		[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
		[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
		[GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
		[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
		[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
		[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
		[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
		[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
		[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
		[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
		[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
		[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
		[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,

include/dt-bindings/clock/qcom,gcc-sdmmagpie.h

+114 −121

Original line number	Diff line number	Diff line
		@@ -63,127 +63,120 @@
		#define GCC_GPU_MEMNOC_GFX_CLK 43
		#define GCC_GPU_SNOC_DVM_GFX_CLK 44
		#define GCC_GPU_VS_CLK 45
		#define GCC_MSS_AXIS2_CLK 46
		#define GCC_MSS_CFG_AHB_CLK 47
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 48
		#define GCC_MSS_MFAB_AXIS_CLK 49
		#define GCC_MSS_Q6_MEMNOC_AXI_CLK 50
		#define GCC_MSS_SNOC_AXI_CLK 51
		#define GCC_MSS_VS_CLK 52
		#define GCC_NPU_AXI_CLK 53
		#define GCC_NPU_CFG_AHB_CLK 54
		#define GCC_NPU_GPLL0_CLK_SRC 55
		#define GCC_NPU_GPLL0_DIV_CLK_SRC 56
		#define GCC_PCIE_0_AUX_CLK 57
		#define GCC_PCIE_0_AUX_CLK_SRC 58
		#define GCC_PCIE_0_CFG_AHB_CLK 59
		#define GCC_PCIE_0_CLKREF_CLK 60
		#define GCC_PCIE_0_MSTR_AXI_CLK 61
		#define GCC_PCIE_0_PIPE_CLK 62
		#define GCC_PCIE_0_SLV_AXI_CLK 63
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 64
		#define GCC_PCIE_PHY_AUX_CLK 65
		#define GCC_PCIE_PHY_REFGEN_CLK 66
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
		#define GCC_PDM2_CLK 68
		#define GCC_PDM2_CLK_SRC 69
		#define GCC_PDM_AHB_CLK 70
		#define GCC_PDM_XO4_CLK 71
		#define GCC_PRNG_AHB_CLK 72
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
		#define GCC_QUPV3_WRAP0_CORE_CLK 74
		#define GCC_QUPV3_WRAP0_S0_CLK 75
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
		#define GCC_QUPV3_WRAP0_S1_CLK 77
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
		#define GCC_QUPV3_WRAP0_S2_CLK 79
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
		#define GCC_QUPV3_WRAP0_S3_CLK 81
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
		#define GCC_QUPV3_WRAP0_S4_CLK 83
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
		#define GCC_QUPV3_WRAP0_S5_CLK 85
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
		#define GCC_QUPV3_WRAP0_S6_CLK 87
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 88
		#define GCC_QUPV3_WRAP0_S7_CLK 89
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 90
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91
		#define GCC_QUPV3_WRAP1_CORE_CLK 92
		#define GCC_QUPV3_WRAP1_S0_CLK 93
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94
		#define GCC_QUPV3_WRAP1_S1_CLK 95
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96
		#define GCC_QUPV3_WRAP1_S2_CLK 97
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98
		#define GCC_QUPV3_WRAP1_S3_CLK 99
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100
		#define GCC_QUPV3_WRAP1_S4_CLK 101
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102
		#define GCC_QUPV3_WRAP1_S5_CLK 103
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104
		#define GCC_QUPV3_WRAP1_S6_CLK 105
		#define GCC_QUPV3_WRAP1_S6_CLK_SRC 106
		#define GCC_QUPV3_WRAP1_S7_CLK 107
		#define GCC_QUPV3_WRAP1_S7_CLK_SRC 108
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 109
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 110
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 111
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 112
		#define GCC_SDCC1_AHB_CLK 113
		#define GCC_SDCC1_APPS_CLK 114
		#define GCC_SDCC1_APPS_CLK_SRC 115
		#define GCC_SDCC1_ICE_CORE_CLK 116
		#define GCC_SDCC1_ICE_CORE_CLK_SRC 117
		#define GCC_SDCC2_AHB_CLK 118
		#define GCC_SDCC2_APPS_CLK 119
		#define GCC_SDCC2_APPS_CLK_SRC 120
		#define GCC_SDCC4_AHB_CLK 121
		#define GCC_SDCC4_APPS_CLK 122
		#define GCC_SDCC4_APPS_CLK_SRC 123
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 124
		#define GCC_TSIF_AHB_CLK 125
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 126
		#define GCC_TSIF_REF_CLK 127
		#define GCC_TSIF_REF_CLK_SRC 128
		#define GCC_UFS_MEM_CLKREF_CLK 129
		#define GCC_UFS_PHY_AHB_CLK 130
		#define GCC_UFS_PHY_AXI_CLK 131
		#define GCC_UFS_PHY_AXI_CLK_SRC 132
		#define GCC_UFS_PHY_AXI_HW_CTL_CLK 133
		#define GCC_UFS_PHY_ICE_CORE_CLK 134
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 135
		#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 136
		#define GCC_UFS_PHY_PHY_AUX_CLK 137
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 138
		#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 139
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 140
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 141
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 142
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 143
		#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 144
		#define GCC_USB30_PRIM_MASTER_CLK 145
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 146
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 147
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 148
		#define GCC_USB30_PRIM_SLEEP_CLK 149
		#define GCC_USB3_PRIM_CLKREF_CLK 150
		#define GCC_USB3_PRIM_PHY_AUX_CLK 151
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 154
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 155
		#define GCC_VDDA_VS_CLK 156
		#define GCC_VDDCX_VS_CLK 157
		#define GCC_VDDMX_VS_CLK 158
		#define GCC_VIDEO_AHB_CLK 159
		#define GCC_VIDEO_AXI_CLK 160
		#define GCC_VIDEO_XO_CLK 161
		#define GCC_VS_CTRL_AHB_CLK 162
		#define GCC_VS_CTRL_CLK 163
		#define GCC_VS_CTRL_CLK_SRC 164
		#define GCC_VSENSOR_CLK_SRC 165
		#define GCC_GPLL0_MAIN_DIV_CDIV 167
		#define GCC_NPU_AXI_CLK 46
		#define GCC_NPU_CFG_AHB_CLK 47
		#define GCC_NPU_GPLL0_CLK_SRC 48
		#define GCC_NPU_GPLL0_DIV_CLK_SRC 49
		#define GCC_PCIE_0_AUX_CLK 50
		#define GCC_PCIE_0_AUX_CLK_SRC 51
		#define GCC_PCIE_0_CFG_AHB_CLK 52
		#define GCC_PCIE_0_CLKREF_CLK 53
		#define GCC_PCIE_0_MSTR_AXI_CLK 54
		#define GCC_PCIE_0_PIPE_CLK 55
		#define GCC_PCIE_0_SLV_AXI_CLK 56
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
		#define GCC_PCIE_PHY_AUX_CLK 58
		#define GCC_PCIE_PHY_REFGEN_CLK 59
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 60
		#define GCC_PDM2_CLK 61
		#define GCC_PDM2_CLK_SRC 62
		#define GCC_PDM_AHB_CLK 63
		#define GCC_PDM_XO4_CLK 64
		#define GCC_PRNG_AHB_CLK 65
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 66
		#define GCC_QUPV3_WRAP0_CORE_CLK 67
		#define GCC_QUPV3_WRAP0_S0_CLK 68
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
		#define GCC_QUPV3_WRAP0_S1_CLK 70
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
		#define GCC_QUPV3_WRAP0_S2_CLK 72
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
		#define GCC_QUPV3_WRAP0_S3_CLK 74
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
		#define GCC_QUPV3_WRAP0_S4_CLK 76
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 78
		#define GCC_QUPV3_WRAP0_S5_CLK 79
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 80
		#define GCC_QUPV3_WRAP0_S6_CLK 81
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 82
		#define GCC_QUPV3_WRAP0_S7_CLK 83
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 84
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 85
		#define GCC_QUPV3_WRAP1_CORE_CLK 86
		#define GCC_QUPV3_WRAP1_S0_CLK 87
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 88
		#define GCC_QUPV3_WRAP1_S1_CLK 89
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 90
		#define GCC_QUPV3_WRAP1_S2_CLK 91
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 92
		#define GCC_QUPV3_WRAP1_S3_CLK 93
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 94
		#define GCC_QUPV3_WRAP1_S4_CLK 95
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 96
		#define GCC_QUPV3_WRAP1_S5_CLK 97
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 98
		#define GCC_QUPV3_WRAP1_S6_CLK 99
		#define GCC_QUPV3_WRAP1_S6_CLK_SRC 100
		#define GCC_QUPV3_WRAP1_S7_CLK 101
		#define GCC_QUPV3_WRAP1_S7_CLK_SRC 102
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 103
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 104
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 105
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 106
		#define GCC_SDCC1_AHB_CLK 107
		#define GCC_SDCC1_APPS_CLK 108
		#define GCC_SDCC1_APPS_CLK_SRC 109
		#define GCC_SDCC1_ICE_CORE_CLK 110
		#define GCC_SDCC1_ICE_CORE_CLK_SRC 111
		#define GCC_SDCC2_AHB_CLK 112
		#define GCC_SDCC2_APPS_CLK 113
		#define GCC_SDCC2_APPS_CLK_SRC 114
		#define GCC_SDCC4_AHB_CLK 115
		#define GCC_SDCC4_APPS_CLK 116
		#define GCC_SDCC4_APPS_CLK_SRC 117
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 118
		#define GCC_TSIF_AHB_CLK 119
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 120
		#define GCC_TSIF_REF_CLK 121
		#define GCC_TSIF_REF_CLK_SRC 123
		#define GCC_UFS_MEM_CLKREF_CLK 124
		#define GCC_UFS_PHY_AHB_CLK 125
		#define GCC_UFS_PHY_AXI_CLK 126
		#define GCC_UFS_PHY_AXI_CLK_SRC 127
		#define GCC_UFS_PHY_AXI_HW_CTL_CLK 128
		#define GCC_UFS_PHY_ICE_CORE_CLK 129
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 130
		#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 131
		#define GCC_UFS_PHY_PHY_AUX_CLK 132
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 133
		#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 134
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 135
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 136
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138
		#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 140
		#define GCC_USB30_PRIM_MASTER_CLK 141
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
		#define GCC_USB30_PRIM_SLEEP_CLK 145
		#define GCC_USB3_PRIM_CLKREF_CLK 146
		#define GCC_USB3_PRIM_PHY_AUX_CLK 147
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 148
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 149
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 150
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 151
		#define GCC_VDDA_VS_CLK 152
		#define GCC_VDDCX_VS_CLK 153
		#define GCC_VDDMX_VS_CLK 154
		#define GCC_VIDEO_AHB_CLK 155
		#define GCC_VIDEO_AXI_CLK 156
		#define GCC_VIDEO_XO_CLK 157
		#define GCC_VS_CTRL_AHB_CLK 158
		#define GCC_VS_CTRL_CLK 159
		#define GCC_VS_CTRL_CLK_SRC 160
		#define GCC_VSENSOR_CLK_SRC 161
		#define GCC_GPLL0_MAIN_DIV_CDIV 162

		/* GCC Resets */
		#define GCC_PCIE_0_BCR 0