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Commit da3de889 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM64: dts: qcs405: add ext mclk support"

parents 42408109 188644e3

Documentation/devicetree/bindings/sound/qcom-audio-dev.txt

+13 −0
Original line number Diff line number Diff line
@@ -1439,6 +1439,19 @@ Optional properties: 
- qcom,csra-devs : List of phandles of all possible CSRA66x0 devices supported for the target

- qcom,csra-aux-dev-prefix : Name prefix in multi-channel configuration for CSRA66x0 device

- qcom,afe-rxtx-lb: AFE RX to TX loopback.

- qcom,ext-mclk-gpio: pinctrl referring to external mclk

- qcom,ext-mclk-src: Device tree node referring to external mclk clock

- #ext-mclk-1-cfg-cells: Number of cells in ext-mclk-1-cfg-* nodes. Must be 6.

- ext-mclk-1 cfg-11p2896: Frequnency table for 11.2896MHz mclk frequnecy.

			  Fields are clock rate, div2x, m, n, d and clock root.

- ext-mclk-1 cfg-12p288: Frequnency table for 12.288MHz mclk frequnecy.

			 Fields are clock rate, div2x, m, n, d and clock root.

- ext-mclk-1 cfg-16p384: Frequnency table for 16.384MHz mclk frequnecy.

			 Fields are clock rate, div2x, m, n, d and clock root.

- ext-mclk-1-cfg-22p5792: Frequency table for 22.5792MHz mclk frequency.

                          Fields are clock rate, div2x, m, n, d and clock root.

- ext-mclk-1 cfg-24p576: Frequnency table for 24.576MHz mclk frequnecy.

			 Fields are clock rate, div2x, m, n, d and clock root.

Example:



	qcs405_snd {

arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -69,6 +69,13 @@ 
		&sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep

		&sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>;

	};



	ext_mclk_1_gpios: ext_mclk_1_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&ext_mclk_1_sck_active>;

		pinctrl-1 = <&ext_mclk_1_sck_sleep>;

	};

};



&q6core {
@@ -140,6 +147,69 @@ 
		"CSRA_F0 IN", "PRI_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default>;



	qcom,ext-mclk-gpio = <&ext_mclk_1_gpios>;

	qcom,ext-mclk-src = <&ep92a6_hdmi_64>;

	#ext-mclk-1-cfg-cells = <6>;

	ext-mclk-1-cfg-11p2896 =

		<  352800    2    1   32   32    3>,

		<  705600    2    1   16   16    3>,

		< 1411200    2    1    8    8    3>,

		< 2822400    8    0    0    0    3>,

		< 5644800    4    0    0    0    3>,

		<11289600    2    0    0    0    3>,

		<22579200    2    2    1    1    3>;

	ext-mclk-1-cfg-12p288 =

		<  256000    2    1   48   48    3>,

		<  384000    2    1   32   32    3>,

		<  512000    2    2   48   48    3>,

		<  768000    2    1   16   16    3>,

		< 1024000    2    1   12   12    3>,

		< 1536000    2    1    8    8    3>,

		< 2048000   12    0    0    0    3>,

		< 3072000    8    0    0    0    3>,

		< 4096000    6    0    0    0    3>,

		< 6144000    4    0    0    0    3>,

		< 8192000    6    2    1    1    3>,

		<12288000   10   10    1    1    3>,

		<15360000   20   25    2    2    3>,

		<24576000   20   20    1    1    3>;

	ext-mclk-1-cfg-16p384 =

		<  256000   32    1    4    4    3>,

		<  384000   32    3    8    8    3>,

		<  512000   32    1    2    2    3>,

		<  768000   32    3    4    4    3>,

		< 1024000   32    0    0    0    3>,

		< 1536000   24    9    8    8    3>,

		< 2048000   16    0    0    0    3>,

		< 3072000   16    3    2    2    3>,

		< 4096000    8    0    0    0    3>,

		< 6144000    8    3    2    2    3>,

		< 8192000    4    0    0    0    3>,

		<12288000    8    3    1    1    3>,

		<24576000    4    3    1    1    3>;

	ext-mclk-1-cfg-22p5792 =

		<  352800    2    1   64   64    3>,

		<  705600    2    1   32   32    3>,

		< 1411200    2    1   16   16    3>,

		< 2822400   16    0    0    0    3>,

		< 5644800    8    0    0    0    3>,

		<11289600    4    0    0    0    3>,

		<22579200    2    0    0    0    3>;

	ext-mclk-1-cfg-24p576 =

		<  256000    2    1   96   96    3>,

		<  384000    2    1   64   64    3>,

		<  512000    2    1   48   48    3>,

		<  768000    2    1   32   32    3>,

		< 1024000    2    1   24   24    3>,

		< 1536000    2    1   16   16    3>,

		< 2048000   24    0    0    0    3>,

		< 3072000   16    0    0    0    3>,

		< 4096000   12    0    0    0    3>,

		< 6144000    8    0    0    0    3>,

		< 8192000    6    0    0    0    3>,

		<12288000    4    0    0    0    3>,

		<24576000    2    0    0    0    3>;

};



&dai_mi2s0 {

arch/arm64/boot/dts/qcom/qcs405-csra8plus2-audio-overlay.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -90,6 +90,13 @@ 
		&quat_mi2s_dsd_d3_active &quat_mi2s_dsd_d4_active

		&quat_mi2s_dsd_d5_active>;

	};



	ext_mclk_1_gpios: ext_mclk_1_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&ext_mclk_1_sck_active>;

		pinctrl-1 = <&ext_mclk_1_sck_sleep>;

	};

};



&q6core {
@@ -168,6 +175,69 @@ 
		"CSRA_F0 IN", "PRI_META_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default>;



	qcom,ext-mclk-gpio = <&ext_mclk_1_gpios>;

	qcom,ext-mclk-src = <&ep92a6_hdmi_64>;

	#ext-mclk-1-cfg-cells = <6>;

	ext-mclk-1-cfg-11p2896 =

		<  352800    2    1   32   32    3>,

		<  705600    2    1   16   16    3>,

		< 1411200    2    1    8    8    3>,

		< 2822400    8    0    0    0    3>,

		< 5644800    4    0    0    0    3>,

		<11289600    2    0    0    0    3>,

		<22579200    2    2    1    1    3>;

	ext-mclk-1-cfg-12p288 =

		<  256000    2    1   48   48    3>,

		<  384000    2    1   32   32    3>,

		<  512000    2    2   48   48    3>,

		<  768000    2    1   16   16    3>,

		< 1024000    2    1   12   12    3>,

		< 1536000    2    1    8    8    3>,

		< 2048000   12    0    0    0    3>,

		< 3072000    8    0    0    0    3>,

		< 4096000    6    0    0    0    3>,

		< 6144000    4    0    0    0    3>,

		< 8192000    6    2    1    1    3>,

		<12288000   10   10    1    1    3>,

		<15360000   20   25    2    2    3>,

		<24576000   20   20    1    1    3>;

	ext-mclk-1-cfg-16p384 =

		<  256000   32    1    4    4    3>,

		<  384000   32    3    8    8    3>,

		<  512000   32    1    2    2    3>,

		<  768000   32    3    4    4    3>,

		< 1024000   32    0    0    0    3>,

		< 1536000   24    9    8    8    3>,

		< 2048000   16    0    0    0    3>,

		< 3072000   16    3    2    2    3>,

		< 4096000    8    0    0    0    3>,

		< 6144000    8    3    2    2    3>,

		< 8192000    4    0    0    0    3>,

		<12288000    8    3    1    1    3>,

		<24576000    4    3    1    1    3>;

	ext-mclk-1-cfg-22p5792 =

		<  352800    2    1   64   64    3>,

		<  705600    2    1   32   32    3>,

		< 1411200    2    1   16   16    3>,

		< 2822400   16    0    0    0    3>,

		< 5644800    8    0    0    0    3>,

		<11289600    4    0    0    0    3>,

		<22579200    2    0    0    0    3>;

	ext-mclk-1-cfg-24p576 =

		<  256000    2    1   96   96    3>,

		<  384000    2    1   64   64    3>,

		<  512000    2    1   48   48    3>,

		<  768000    2    1   32   32    3>,

		< 1024000    2    1   24   24    3>,

		< 1536000    2    1   16   16    3>,

		< 2048000   24    0    0    0    3>,

		< 3072000   16    0    0    0    3>,

		< 4096000   12    0    0    0    3>,

		< 6144000    8    0    0    0    3>,

		< 8192000    6    0    0    0    3>,

		<12288000    4    0    0    0    3>,

		<24576000    2    0    0    0    3>;

};



&dai_mi2s0 {

arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi

+31 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -2837,6 +2837,36 @@ 
			};

		};



		ext_mclk_1 {

			ext_mclk_1_sck_sleep: ext_mclk_1_sck_sleep {

				mux {

					pins = "gpio103";

					function = "mclk_in2";

				};



				config {

					pins = "gpio103";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

				};

			};



			ext_mclk_1_sck_active: ext_mclk_1_sck_active {

				mux {

					pins = "gpio103";

					function = "mclk_in2";

				};



				config {

					pins = "gpio103";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

					input-enable;

				};

			};

		};





		/* SPDIF optical input pin */

		spdifrx_opt {

			spdifrx_opt_default: spdifrx_opt_default {