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Commit d9c3f5df authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Chris Ball
Browse files

dts: socfpga: Add support for SD/MMC on the SOCFPGA platform 



Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.

Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Acked-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent ec1e5d70

Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

0 → 100644
+23 −0
Original line number Diff line number Diff line 
* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile

  Storage Host Controller



The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific

extensions to the Synopsys Designware Mobile Storage Host Controller.



Required Properties:



* compatible: should be

	- "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform



Example:



	mmc: dwmmc0@ff704000 {

		compatible = "altr,socfpga-dw-mshc";

		reg = <0xff704000 0x1000>;

		interrupts = <0 129 4>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

arch/arm/boot/dts/socfpga.dtsi

+14 −3
Original line number Diff line number Diff line
@@ -473,6 +473,17 @@ 
			arm,data-latency = <2 1 1>;

		};



		mmc: dwmmc0@ff704000 {

			compatible = "altr,socfpga-dw-mshc";

			reg = <0xff704000 0x1000>;

			interrupts = <0 139 4>;

			fifo-depth = <0x400>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&l4_mp_clk>, <&sdmmc_clk>;

			clock-names = "biu", "ciu";

		};



		/* Local timer */

		timer@fffec600 {

			compatible = "arm,cortex-a9-twd-timer";
@@ -527,7 +538,7 @@ 
		};



		sysmgr@ffd08000 {

				compatible = "altr,sys-mgr";

			compatible = "altr,sys-mgr", "syscon";

			reg = <0xffd08000 0x4000>;

		};

	};

arch/arm/boot/dts/socfpga_arria5.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -27,6 +27,17 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};

arch/arm/boot/dts/socfpga_cyclone5.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -28,6 +28,17 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		ethernet@ff702000 {

			phy-mode = "rgmii";

			phy-addr = <0xffffffff>; /* probe for phy addr */

arch/arm/boot/dts/socfpga_vt.dts

+11 −0
Original line number Diff line number Diff line
@@ -41,6 +41,17 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		ethernet@ff700000 {

			phy-mode = "gmii";

			status = "okay";