Loading drivers/cpufreq/qcom-cpufreq-hw.c +248 −223 Original line number Original line Diff line number Diff line Loading @@ -3,43 +3,44 @@ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ */ #include <linux/bitfield.h> #include <linux/cpufreq.h> #include <linux/cpufreq.h> #include <linux/cpu_cooling.h> #include <linux/energy_model.h> #include <linux/init.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/of_platform.h> #include <linux/pm_opp.h> #include <linux/pm_opp.h> #include <linux/energy_model.h> #include <linux/sched.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/cpu_cooling.h> #define LUT_MAX_ENTRIES 40U #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) #define CORE_COUNT_VAL(val) (((val) & (GENMASK(18, 16))) >> 16) #define LUT_L_VAL GENMASK(7, 0) #define LUT_CORE_COUNT GENMASK(18, 16) #define LUT_VOLT GENMASK(11, 0) #define LUT_ROW_SIZE 32 #define LUT_ROW_SIZE 32 #define CLK_HW_DIV 2 #define CLK_HW_DIV 2 #define CYCLE_CNTR_OFFSET(c, m) ((c - cpumask_first(m) + 1) * 4) #define CYCLE_CNTR_OFFSET(c, m) ((c - cpumask_first(m) + 1) * 4) enum { enum { REG_ENABLE, REG_ENABLE, REG_FREQ_LUT, REG_FREQ_LUT_TABLE, REG_VOLT_LUT, REG_VOLT_LUT_TABLE, REG_PERF_STATE, REG_PERF_STATE, REG_CYCLE_CNTR, REG_CYCLE_CNTR, REG_ARRAY_SIZE, REG_ARRAY_SIZE, }; }; static unsigned long cpu_hw_rate, xo_rate; static struct platform_device *global_pdev; static const u16 *offsets; static unsigned int lut_row_size = LUT_ROW_SIZE; static unsigned int lut_row_size = LUT_ROW_SIZE; struct cpufreq_qcom { struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; cpumask_t related_cpus; unsigned int max_cores; unsigned long xo_rate; unsigned long cpu_hw_rate; }; struct cpufreq_counter { struct cpufreq_counter { u64 total_cycle_counter; u64 total_cycle_counter; u32 prev_cycle_counter; u32 prev_cycle_counter; Loading @@ -48,41 +49,39 @@ struct cpufreq_counter { static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = { static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = { [REG_ENABLE] = 0x0, [REG_ENABLE] = 0x0, [REG_FREQ_LUT] = 0x110, [REG_FREQ_LUT_TABLE] = 0x110, [REG_VOLT_LUT] = 0x114, [REG_VOLT_LUT_TABLE] = 0x114, [REG_PERF_STATE] = 0x920, [REG_PERF_STATE] = 0x920, [REG_CYCLE_CNTR] = 0x9c0, [REG_CYCLE_CNTR] = 0x9c0, }; }; static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = { static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = { [REG_ENABLE] = 0x0, [REG_ENABLE] = 0x0, [REG_FREQ_LUT] = 0x100, [REG_FREQ_LUT_TABLE] = 0x100, [REG_VOLT_LUT] = 0x200, [REG_VOLT_LUT_TABLE] = 0x200, [REG_PERF_STATE] = 0x320, [REG_PERF_STATE] = 0x320, [REG_CYCLE_CNTR] = 0x3c4, [REG_CYCLE_CNTR] = 0x3c4, }; }; static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS]; static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS]; static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS]; static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) { { struct cpufreq_counter *cpu_counter; struct cpufreq_counter *cpu_counter; struct cpufreq_policy *policy; struct cpufreq_qcom *cpu_domain; u64 cycle_counter_ret; u64 cycle_counter_ret; unsigned long flags; unsigned long flags; u16 offset; u16 offset; u32 val; u32 val; policy = cpufreq_cpu_get_raw(cpu); cpu_domain = qcom_freq_domain_map[cpu]; if (!policy) return 0; cpu_counter = &qcom_cpufreq_counter[cpu]; cpu_counter = &qcom_cpufreq_counter[cpu]; spin_lock_irqsave(&cpu_counter->lock, flags); spin_lock_irqsave(&cpu_counter->lock, flags); offset = CYCLE_CNTR_OFFSET(cpu, policy->related_cpus); offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus); val = readl_relaxed_no_log(policy->driver_data + val = readl_relaxed_no_log(cpu_domain->reg_bases[REG_CYCLE_CNTR] + offsets[REG_CYCLE_CNTR] + offset); offset); if (val < cpu_counter->prev_cycle_counter) { if (val < cpu_counter->prev_cycle_counter) { /* Handle counter overflow */ /* Handle counter overflow */ Loading @@ -94,7 +93,6 @@ static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) cpu_counter->prev_cycle_counter; cpu_counter->prev_cycle_counter; cpu_counter->prev_cycle_counter = val; cpu_counter->prev_cycle_counter = val; } } cycle_counter_ret = cpu_counter->total_cycle_counter; cycle_counter_ret = cpu_counter->total_cycle_counter; spin_unlock_irqrestore(&cpu_counter->lock, flags); spin_unlock_irqrestore(&cpu_counter->lock, flags); Loading @@ -105,9 +103,9 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) unsigned int index) { { void __iomem *perf_state_reg = policy->driver_data; struct cpufreq_qcom *c = policy->driver_data; writel_relaxed(index, perf_state_reg + offsets[REG_PERF_STATE]); writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); arch_set_freq_scale(policy->related_cpus, arch_set_freq_scale(policy->related_cpus, policy->freq_table[index].frequency, policy->freq_table[index].frequency, policy->cpuinfo.max_freq); policy->cpuinfo.max_freq); Loading @@ -117,7 +115,7 @@ qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) { { void __iomem *perf_state_reg; struct cpufreq_qcom *c; struct cpufreq_policy *policy; struct cpufreq_policy *policy; unsigned int index; unsigned int index; Loading @@ -125,9 +123,9 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) if (!policy) if (!policy) return 0; return 0; perf_state_reg = policy->driver_data + offsets[REG_PERF_STATE]; c = policy->driver_data; index = readl_relaxed(perf_state_reg); index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); index = min(index, LUT_MAX_ENTRIES - 1); index = min(index, LUT_MAX_ENTRIES - 1); return policy->freq_table[index].frequency; return policy->freq_table[index].frequency; Loading @@ -149,74 +147,155 @@ qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, return policy->freq_table[index].frequency; return policy->freq_table[index].frequency; } } static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct cpufreq_policy *policy, u32 max_cores) { { u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq; struct em_data_callback em_cb = EM_DATA_CB(of_dev_pm_opp_get_cpu_power); u32 volt; struct cpufreq_qcom *c; struct cpufreq_frequency_table *table; struct device *cpu_dev; void __iomem *base = policy->driver_data; int ret; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); return -ENODEV; } c = qcom_freq_domain_map[policy->cpu]; if (!c) { pr_err("No scaling support for CPU%d\n", policy->cpu); return -ENODEV; } cpumask_copy(policy->cpus, &c->related_cpus); ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) dev_err(cpu_dev, "OPP table is not ready\n"); table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); policy->fast_switch_possible = true; if (!table) policy->freq_table = c->table; policy->driver_data = c; policy->dvfs_possible_from_any_cpu = true; em_register_perf_domain(policy->cpus, ret, &em_cb); return 0; } static struct freq_attr *qcom_cpufreq_hw_attr[] = { &cpufreq_freq_attr_scaling_available_freqs, &cpufreq_freq_attr_scaling_boost_freqs, NULL }; static void qcom_cpufreq_ready(struct cpufreq_policy *policy) { static struct thermal_cooling_device *cdev[NR_CPUS]; struct device_node *np; unsigned int cpu = policy->cpu; if (cdev[cpu]) return; np = of_cpu_device_node_get(cpu); if (WARN_ON(!np)) return; /* * For now, just loading the cooling device; * thermal DT code takes care of matching them. */ if (of_find_property(np, "#cooling-cells", NULL)) { cdev[cpu] = of_cpufreq_cooling_register(policy); if (IS_ERR(cdev[cpu])) { pr_err("running cpufreq for CPU%d without cooling dev: %ld\n", cpu, PTR_ERR(cdev[cpu])); cdev[cpu] = NULL; } } of_node_put(np); } static struct cpufreq_driver cpufreq_qcom_hw_driver = { .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, .verify = cpufreq_generic_frequency_table_verify, .target_index = qcom_cpufreq_hw_target_index, .get = qcom_cpufreq_hw_get, .init = qcom_cpufreq_hw_cpu_init, .fast_switch = qcom_cpufreq_hw_fast_switch, .name = "qcom-cpufreq-hw", .attr = qcom_cpufreq_hw_attr, .boost_enabled = true, .ready = qcom_cpufreq_ready, }; static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev, struct cpufreq_qcom *c) { struct device *dev = &pdev->dev; void __iomem *base_freq, *base_volt; u32 data, src, lval, i, core_count, prev_cc, prev_freq, cur_freq, volt; unsigned long cpu; c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1, sizeof(*c->table), GFP_KERNEL); if (!c->table) return -ENOMEM; return -ENOMEM; base_freq = c->reg_bases[REG_FREQ_LUT_TABLE]; base_volt = c->reg_bases[REG_VOLT_LUT_TABLE]; for (i = 0; i < LUT_MAX_ENTRIES; i++) { for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base + offsets[REG_FREQ_LUT] + data = readl_relaxed(base_freq + i * lut_row_size); i * lut_row_size); src = (data & GENMASK(31, 30)) >> 30; src = FIELD_GET(LUT_SRC, data); lval = data & GENMASK(7, 0); lval = FIELD_GET(LUT_L_VAL, data); core_count = CORE_COUNT_VAL(data); core_count = FIELD_GET(LUT_CORE_COUNT, data); data = readl_relaxed(base + offsets[REG_VOLT_LUT] + data = readl_relaxed(base_volt + i * lut_row_size); i * lut_row_size); volt = (data & GENMASK(11, 0)) * 1000; volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) if (src) freq = xo_rate * lval / 1000; c->table[i].frequency = c->xo_rate * lval / 1000; else else freq = cpu_hw_rate / 1000; c->table[i].frequency = c->cpu_hw_rate / 1000; if (freq != prev_freq && core_count == max_cores) { cur_freq = c->table[i].frequency; table[i].frequency = freq; dev_pm_opp_add(cpu_dev, freq * 1000, volt); dev_dbg(dev, "index=%d freq=%d, core_count %d\n", dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, i, c->table[i].frequency, core_count); freq, core_count); } else { if (core_count != c->max_cores) table[i].frequency = CPUFREQ_ENTRY_INVALID; cur_freq = CPUFREQ_ENTRY_INVALID; } /* /* * Two of the same frequencies with the same core counts means * Two of the same frequencies with the same core counts means * end of table. * end of table. */ */ if (i > 0 && prev_freq == freq && prev_cc == core_count) { if (i > 0 && c->table[i - 1].frequency == struct cpufreq_frequency_table *prev = &table[i - 1]; c->table[i].frequency && prev_cc == core_count) { struct cpufreq_frequency_table *prev = &c->table[i - 1]; if (prev_cc != max_cores) { if (prev_freq == CPUFREQ_ENTRY_INVALID) prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; prev->flags = CPUFREQ_BOOST_FREQ; dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt); } break; break; } } prev_cc = core_count; prev_cc = core_count; prev_freq = freq; prev_freq = cur_freq; freq *= 1000; cur_freq *= 1000; for_each_cpu(cpu, &c->related_cpus) dev_pm_opp_add(get_cpu_device(cpu), cur_freq, volt); } } table[i].frequency = CPUFREQ_TABLE_END; c->table[i].frequency = CPUFREQ_TABLE_END; policy->freq_table = table; dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); return 0; return 0; } } static void qcom_get_related_cpus(int index, struct cpumask *m) static int qcom_get_related_cpus(int index, struct cpumask *m) { { struct device_node *cpu_np; struct device_node *cpu_np; struct of_phandle_args args; struct of_phandle_args args; Loading @@ -228,8 +307,7 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) continue; continue; ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", "#freq-domain-cells", 0, "#freq-domain-cells", 0, &args); &args); of_node_put(cpu_np); of_node_put(cpu_np); if (ret < 0) if (ret < 0) continue; continue; Loading @@ -237,201 +315,157 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) if (index == args.args[0]) if (index == args.args[0]) cpumask_set_cpu(cpu, m); cpumask_set_cpu(cpu, m); } } return 0; } } static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) static int qcom_cpu_resources_init(struct platform_device *pdev, unsigned int cpu, int index, unsigned int max_cores, unsigned long xo_rate, unsigned long cpu_hw_rate) { { struct device *dev = &global_pdev->dev; struct cpufreq_qcom *c; struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; struct resource *res; struct resource *res; struct device *dev = &pdev->dev; const u16 *offsets; int ret, i, cpu_r; void __iomem *base; void __iomem *base; int ret, index; cpu_dev = get_cpu_device(policy->cpu); if (qcom_freq_domain_map[cpu]) if (!cpu_dev) { return 0; pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); return -ENODEV; } cpu_np = of_cpu_device_node_get(policy->cpu); if (!cpu_np) return -EINVAL; ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", "#freq-domain-cells", 0, &args); of_node_put(cpu_np); if (ret) return ret; index = args.args[0]; res = platform_get_resource(global_pdev, IORESOURCE_MEM, index); if (!res) return -ENODEV; base = devm_ioremap(dev, res->start, resource_size(res)); c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); if (!base) if (!c) return -ENOMEM; return -ENOMEM; offsets = of_device_get_match_data(dev); offsets = of_device_get_match_data(&pdev->dev); if (!offsets) if (!offsets) return -EINVAL; return -EINVAL; res = platform_get_resource(pdev, IORESOURCE_MEM, index); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) return PTR_ERR(base); for (i = REG_ENABLE; i < REG_ARRAY_SIZE; i++) c->reg_bases[i] = base + offsets[i]; if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) { if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) { /* HW should be in enabled state to proceed */ /* HW should be in enabled state to proceed */ if (!(readl_relaxed(base + offsets[REG_ENABLE]) & 0x1)) { if (!(readl_relaxed(c->reg_bases[REG_ENABLE]) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); index); return -ENODEV; return -ENODEV; } } } } qcom_get_related_cpus(index, policy->cpus); ret = qcom_get_related_cpus(index, &c->related_cpus); if (!cpumask_weight(policy->cpus)) { if (ret) { dev_err(dev, "Domain-%d failed to get related CPUs\n", index); dev_err(dev, "Domain-%d failed to get related CPUs\n", index); ret = -ENOENT; return ret; goto error; } } policy->driver_data = base; c->max_cores = max_cores; if (!c->max_cores) return -ENOENT; ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, args.args[1]); c->xo_rate = xo_rate; c->cpu_hw_rate = cpu_hw_rate; ret = qcom_cpufreq_hw_read_lut(pdev, c); if (ret) { if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); dev_err(dev, "Domain-%d failed to read LUT\n", index); goto error; } ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) { dev_err(cpu_dev, "Failed to add OPPs\n"); ret = -ENODEV; goto error; } dev_pm_opp_of_register_em(policy->cpus); policy->fast_switch_possible = true; policy->dvfs_possible_from_any_cpu = true; return 0; error: devm_iounmap(dev, base); return ret; return ret; } } static void qcom_cpufreq_ready(struct cpufreq_policy *policy) for_each_cpu(cpu_r, &c->related_cpus) { qcom_freq_domain_map[cpu_r] = c; static struct thermal_cooling_device *cdev[NR_CPUS]; struct device_node *np; unsigned int cpu = policy->cpu; if (cdev[cpu]) return; np = of_cpu_device_node_get(cpu); if (WARN_ON(!np)) return; /* * For now, just loading the cooling device; * thermal DT code takes care of matching them. */ if (of_find_property(np, "#cooling-cells", NULL)) { cdev[cpu] = of_cpufreq_cooling_register(policy); if (IS_ERR(cdev[cpu])) { pr_err("running cpufreq for CPU%d without cooling dev: %ld\n", cpu, PTR_ERR(cdev[cpu])); cdev[cpu] = NULL; } } of_node_put(np); } static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { struct device *cpu_dev = get_cpu_device(policy->cpu); void __iomem *base = policy->driver_data; dev_pm_opp_remove_all_dynamic(cpu_dev); kfree(policy->freq_table); devm_iounmap(&global_pdev->dev, base); return 0; return 0; } } static struct freq_attr *qcom_cpufreq_hw_attr[] = { static int qcom_resources_init(struct platform_device *pdev) &cpufreq_freq_attr_scaling_available_freqs, &cpufreq_freq_attr_scaling_boost_freqs, NULL }; static struct cpufreq_driver cpufreq_qcom_hw_driver = { .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, .verify = cpufreq_generic_frequency_table_verify, .target_index = qcom_cpufreq_hw_target_index, .get = qcom_cpufreq_hw_get, .init = qcom_cpufreq_hw_cpu_init, .exit = qcom_cpufreq_hw_cpu_exit, .fast_switch = qcom_cpufreq_hw_fast_switch, .name = "qcom-cpufreq-hw", .attr = qcom_cpufreq_hw_attr, .boost_enabled = true, .ready = qcom_cpufreq_ready, }; static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { { struct cpu_cycle_counter_cb cycle_counter_cb = { struct device_node *cpu_np; .get_cpu_cycle_counter = qcom_cpufreq_get_cpu_cycle_counter, struct of_phandle_args args; }; struct clk *clk; struct clk *clk; unsigned int cpu; unsigned long xo_rate, cpu_hw_rate; int ret; int ret; clk = clk_get(&pdev->dev, "xo"); clk = devm_clk_get(&pdev->dev, "xo"); if (IS_ERR(clk)) if (IS_ERR(clk)) return PTR_ERR(clk); return PTR_ERR(clk); xo_rate = clk_get_rate(clk); xo_rate = clk_get_rate(clk); clk_put(clk); clk = clk_get(&pdev->dev, "alternate"); devm_clk_put(&pdev->dev, clk); clk = devm_clk_get(&pdev->dev, "alternate"); if (IS_ERR(clk)) if (IS_ERR(clk)) return PTR_ERR(clk); return PTR_ERR(clk); cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; clk_put(clk); devm_clk_put(&pdev->dev, clk); of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size", of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size", &lut_row_size); &lut_row_size); global_pdev = pdev; for_each_possible_cpu(cpu) { cpu_np = of_cpu_device_node_get(cpu); if (!cpu_np) { dev_dbg(&pdev->dev, "Failed to get cpu %d device\n", cpu); continue; } ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", if (ret) { "#freq-domain-cells", 0, &args); dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); if (ret < 0) return ret; return ret; } ret = register_cpu_cycle_counter_cb(&cycle_counter_cb); ret = qcom_cpu_resources_init(pdev, cpu, args.args[0], if (ret) { args.args[1], xo_rate, dev_err(&pdev->dev, "cycle counter cb failed to register\n"); cpu_hw_rate); if (ret) return ret; return ret; } } of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); return 0; dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); return ret; } } static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { { return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); int rc; struct cpu_cycle_counter_cb cycle_counter_cb = { .get_cpu_cycle_counter = qcom_cpufreq_get_cpu_cycle_counter, }; /* Get the bases of cpufreq for domains */ rc = qcom_resources_init(pdev); if (rc) { dev_err(&pdev->dev, "CPUFreq resource init failed\n"); return rc; } rc = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (rc) { dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); return rc; } rc = register_cpu_cycle_counter_cb(&cycle_counter_cb); if (rc) { dev_err(&pdev->dev, "cycle counter cb failed to register\n"); return rc; } dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); return 0; } } static const struct of_device_id qcom_cpufreq_hw_match[] = { static const struct of_device_id qcom_cpufreq_hw_match[] = { Loading @@ -440,11 +474,9 @@ static const struct of_device_id qcom_cpufreq_hw_match[] = { .data = &cpufreq_qcom_epss_std_offsets }, .data = &cpufreq_qcom_epss_std_offsets }, {} {} }; }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); static struct platform_driver qcom_cpufreq_hw_driver = { static struct platform_driver qcom_cpufreq_hw_driver = { .probe = qcom_cpufreq_hw_driver_probe, .probe = qcom_cpufreq_hw_driver_probe, .remove = qcom_cpufreq_hw_driver_remove, .driver = { .driver = { .name = "qcom-cpufreq-hw", .name = "qcom-cpufreq-hw", .of_match_table = qcom_cpufreq_hw_match, .of_match_table = qcom_cpufreq_hw_match, Loading @@ -457,11 +489,4 @@ static int __init qcom_cpufreq_hw_init(void) } } subsys_initcall(qcom_cpufreq_hw_init); subsys_initcall(qcom_cpufreq_hw_init); static void __exit qcom_cpufreq_hw_exit(void) MODULE_DESCRIPTION("QCOM firmware-based CPU Frequency driver"); { platform_driver_unregister(&qcom_cpufreq_hw_driver); } module_exit(qcom_cpufreq_hw_exit); MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); MODULE_LICENSE("GPL v2"); Loading
drivers/cpufreq/qcom-cpufreq-hw.c +248 −223 Original line number Original line Diff line number Diff line Loading @@ -3,43 +3,44 @@ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ */ #include <linux/bitfield.h> #include <linux/cpufreq.h> #include <linux/cpufreq.h> #include <linux/cpu_cooling.h> #include <linux/energy_model.h> #include <linux/init.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/of_platform.h> #include <linux/pm_opp.h> #include <linux/pm_opp.h> #include <linux/energy_model.h> #include <linux/sched.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/cpu_cooling.h> #define LUT_MAX_ENTRIES 40U #define LUT_MAX_ENTRIES 40U #define LUT_SRC GENMASK(31, 30) #define CORE_COUNT_VAL(val) (((val) & (GENMASK(18, 16))) >> 16) #define LUT_L_VAL GENMASK(7, 0) #define LUT_CORE_COUNT GENMASK(18, 16) #define LUT_VOLT GENMASK(11, 0) #define LUT_ROW_SIZE 32 #define LUT_ROW_SIZE 32 #define CLK_HW_DIV 2 #define CLK_HW_DIV 2 #define CYCLE_CNTR_OFFSET(c, m) ((c - cpumask_first(m) + 1) * 4) #define CYCLE_CNTR_OFFSET(c, m) ((c - cpumask_first(m) + 1) * 4) enum { enum { REG_ENABLE, REG_ENABLE, REG_FREQ_LUT, REG_FREQ_LUT_TABLE, REG_VOLT_LUT, REG_VOLT_LUT_TABLE, REG_PERF_STATE, REG_PERF_STATE, REG_CYCLE_CNTR, REG_CYCLE_CNTR, REG_ARRAY_SIZE, REG_ARRAY_SIZE, }; }; static unsigned long cpu_hw_rate, xo_rate; static struct platform_device *global_pdev; static const u16 *offsets; static unsigned int lut_row_size = LUT_ROW_SIZE; static unsigned int lut_row_size = LUT_ROW_SIZE; struct cpufreq_qcom { struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; cpumask_t related_cpus; unsigned int max_cores; unsigned long xo_rate; unsigned long cpu_hw_rate; }; struct cpufreq_counter { struct cpufreq_counter { u64 total_cycle_counter; u64 total_cycle_counter; u32 prev_cycle_counter; u32 prev_cycle_counter; Loading @@ -48,41 +49,39 @@ struct cpufreq_counter { static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = { static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = { [REG_ENABLE] = 0x0, [REG_ENABLE] = 0x0, [REG_FREQ_LUT] = 0x110, [REG_FREQ_LUT_TABLE] = 0x110, [REG_VOLT_LUT] = 0x114, [REG_VOLT_LUT_TABLE] = 0x114, [REG_PERF_STATE] = 0x920, [REG_PERF_STATE] = 0x920, [REG_CYCLE_CNTR] = 0x9c0, [REG_CYCLE_CNTR] = 0x9c0, }; }; static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = { static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = { [REG_ENABLE] = 0x0, [REG_ENABLE] = 0x0, [REG_FREQ_LUT] = 0x100, [REG_FREQ_LUT_TABLE] = 0x100, [REG_VOLT_LUT] = 0x200, [REG_VOLT_LUT_TABLE] = 0x200, [REG_PERF_STATE] = 0x320, [REG_PERF_STATE] = 0x320, [REG_CYCLE_CNTR] = 0x3c4, [REG_CYCLE_CNTR] = 0x3c4, }; }; static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS]; static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS]; static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS]; static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) { { struct cpufreq_counter *cpu_counter; struct cpufreq_counter *cpu_counter; struct cpufreq_policy *policy; struct cpufreq_qcom *cpu_domain; u64 cycle_counter_ret; u64 cycle_counter_ret; unsigned long flags; unsigned long flags; u16 offset; u16 offset; u32 val; u32 val; policy = cpufreq_cpu_get_raw(cpu); cpu_domain = qcom_freq_domain_map[cpu]; if (!policy) return 0; cpu_counter = &qcom_cpufreq_counter[cpu]; cpu_counter = &qcom_cpufreq_counter[cpu]; spin_lock_irqsave(&cpu_counter->lock, flags); spin_lock_irqsave(&cpu_counter->lock, flags); offset = CYCLE_CNTR_OFFSET(cpu, policy->related_cpus); offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus); val = readl_relaxed_no_log(policy->driver_data + val = readl_relaxed_no_log(cpu_domain->reg_bases[REG_CYCLE_CNTR] + offsets[REG_CYCLE_CNTR] + offset); offset); if (val < cpu_counter->prev_cycle_counter) { if (val < cpu_counter->prev_cycle_counter) { /* Handle counter overflow */ /* Handle counter overflow */ Loading @@ -94,7 +93,6 @@ static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) cpu_counter->prev_cycle_counter; cpu_counter->prev_cycle_counter; cpu_counter->prev_cycle_counter = val; cpu_counter->prev_cycle_counter = val; } } cycle_counter_ret = cpu_counter->total_cycle_counter; cycle_counter_ret = cpu_counter->total_cycle_counter; spin_unlock_irqrestore(&cpu_counter->lock, flags); spin_unlock_irqrestore(&cpu_counter->lock, flags); Loading @@ -105,9 +103,9 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) unsigned int index) { { void __iomem *perf_state_reg = policy->driver_data; struct cpufreq_qcom *c = policy->driver_data; writel_relaxed(index, perf_state_reg + offsets[REG_PERF_STATE]); writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); arch_set_freq_scale(policy->related_cpus, arch_set_freq_scale(policy->related_cpus, policy->freq_table[index].frequency, policy->freq_table[index].frequency, policy->cpuinfo.max_freq); policy->cpuinfo.max_freq); Loading @@ -117,7 +115,7 @@ qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) { { void __iomem *perf_state_reg; struct cpufreq_qcom *c; struct cpufreq_policy *policy; struct cpufreq_policy *policy; unsigned int index; unsigned int index; Loading @@ -125,9 +123,9 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) if (!policy) if (!policy) return 0; return 0; perf_state_reg = policy->driver_data + offsets[REG_PERF_STATE]; c = policy->driver_data; index = readl_relaxed(perf_state_reg); index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); index = min(index, LUT_MAX_ENTRIES - 1); index = min(index, LUT_MAX_ENTRIES - 1); return policy->freq_table[index].frequency; return policy->freq_table[index].frequency; Loading @@ -149,74 +147,155 @@ qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, return policy->freq_table[index].frequency; return policy->freq_table[index].frequency; } } static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct cpufreq_policy *policy, u32 max_cores) { { u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq; struct em_data_callback em_cb = EM_DATA_CB(of_dev_pm_opp_get_cpu_power); u32 volt; struct cpufreq_qcom *c; struct cpufreq_frequency_table *table; struct device *cpu_dev; void __iomem *base = policy->driver_data; int ret; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); return -ENODEV; } c = qcom_freq_domain_map[policy->cpu]; if (!c) { pr_err("No scaling support for CPU%d\n", policy->cpu); return -ENODEV; } cpumask_copy(policy->cpus, &c->related_cpus); ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) dev_err(cpu_dev, "OPP table is not ready\n"); table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); policy->fast_switch_possible = true; if (!table) policy->freq_table = c->table; policy->driver_data = c; policy->dvfs_possible_from_any_cpu = true; em_register_perf_domain(policy->cpus, ret, &em_cb); return 0; } static struct freq_attr *qcom_cpufreq_hw_attr[] = { &cpufreq_freq_attr_scaling_available_freqs, &cpufreq_freq_attr_scaling_boost_freqs, NULL }; static void qcom_cpufreq_ready(struct cpufreq_policy *policy) { static struct thermal_cooling_device *cdev[NR_CPUS]; struct device_node *np; unsigned int cpu = policy->cpu; if (cdev[cpu]) return; np = of_cpu_device_node_get(cpu); if (WARN_ON(!np)) return; /* * For now, just loading the cooling device; * thermal DT code takes care of matching them. */ if (of_find_property(np, "#cooling-cells", NULL)) { cdev[cpu] = of_cpufreq_cooling_register(policy); if (IS_ERR(cdev[cpu])) { pr_err("running cpufreq for CPU%d without cooling dev: %ld\n", cpu, PTR_ERR(cdev[cpu])); cdev[cpu] = NULL; } } of_node_put(np); } static struct cpufreq_driver cpufreq_qcom_hw_driver = { .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, .verify = cpufreq_generic_frequency_table_verify, .target_index = qcom_cpufreq_hw_target_index, .get = qcom_cpufreq_hw_get, .init = qcom_cpufreq_hw_cpu_init, .fast_switch = qcom_cpufreq_hw_fast_switch, .name = "qcom-cpufreq-hw", .attr = qcom_cpufreq_hw_attr, .boost_enabled = true, .ready = qcom_cpufreq_ready, }; static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev, struct cpufreq_qcom *c) { struct device *dev = &pdev->dev; void __iomem *base_freq, *base_volt; u32 data, src, lval, i, core_count, prev_cc, prev_freq, cur_freq, volt; unsigned long cpu; c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1, sizeof(*c->table), GFP_KERNEL); if (!c->table) return -ENOMEM; return -ENOMEM; base_freq = c->reg_bases[REG_FREQ_LUT_TABLE]; base_volt = c->reg_bases[REG_VOLT_LUT_TABLE]; for (i = 0; i < LUT_MAX_ENTRIES; i++) { for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base + offsets[REG_FREQ_LUT] + data = readl_relaxed(base_freq + i * lut_row_size); i * lut_row_size); src = (data & GENMASK(31, 30)) >> 30; src = FIELD_GET(LUT_SRC, data); lval = data & GENMASK(7, 0); lval = FIELD_GET(LUT_L_VAL, data); core_count = CORE_COUNT_VAL(data); core_count = FIELD_GET(LUT_CORE_COUNT, data); data = readl_relaxed(base + offsets[REG_VOLT_LUT] + data = readl_relaxed(base_volt + i * lut_row_size); i * lut_row_size); volt = (data & GENMASK(11, 0)) * 1000; volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) if (src) freq = xo_rate * lval / 1000; c->table[i].frequency = c->xo_rate * lval / 1000; else else freq = cpu_hw_rate / 1000; c->table[i].frequency = c->cpu_hw_rate / 1000; if (freq != prev_freq && core_count == max_cores) { cur_freq = c->table[i].frequency; table[i].frequency = freq; dev_pm_opp_add(cpu_dev, freq * 1000, volt); dev_dbg(dev, "index=%d freq=%d, core_count %d\n", dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, i, c->table[i].frequency, core_count); freq, core_count); } else { if (core_count != c->max_cores) table[i].frequency = CPUFREQ_ENTRY_INVALID; cur_freq = CPUFREQ_ENTRY_INVALID; } /* /* * Two of the same frequencies with the same core counts means * Two of the same frequencies with the same core counts means * end of table. * end of table. */ */ if (i > 0 && prev_freq == freq && prev_cc == core_count) { if (i > 0 && c->table[i - 1].frequency == struct cpufreq_frequency_table *prev = &table[i - 1]; c->table[i].frequency && prev_cc == core_count) { struct cpufreq_frequency_table *prev = &c->table[i - 1]; if (prev_cc != max_cores) { if (prev_freq == CPUFREQ_ENTRY_INVALID) prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; prev->flags = CPUFREQ_BOOST_FREQ; dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt); } break; break; } } prev_cc = core_count; prev_cc = core_count; prev_freq = freq; prev_freq = cur_freq; freq *= 1000; cur_freq *= 1000; for_each_cpu(cpu, &c->related_cpus) dev_pm_opp_add(get_cpu_device(cpu), cur_freq, volt); } } table[i].frequency = CPUFREQ_TABLE_END; c->table[i].frequency = CPUFREQ_TABLE_END; policy->freq_table = table; dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); return 0; return 0; } } static void qcom_get_related_cpus(int index, struct cpumask *m) static int qcom_get_related_cpus(int index, struct cpumask *m) { { struct device_node *cpu_np; struct device_node *cpu_np; struct of_phandle_args args; struct of_phandle_args args; Loading @@ -228,8 +307,7 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) continue; continue; ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", "#freq-domain-cells", 0, "#freq-domain-cells", 0, &args); &args); of_node_put(cpu_np); of_node_put(cpu_np); if (ret < 0) if (ret < 0) continue; continue; Loading @@ -237,201 +315,157 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) if (index == args.args[0]) if (index == args.args[0]) cpumask_set_cpu(cpu, m); cpumask_set_cpu(cpu, m); } } return 0; } } static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) static int qcom_cpu_resources_init(struct platform_device *pdev, unsigned int cpu, int index, unsigned int max_cores, unsigned long xo_rate, unsigned long cpu_hw_rate) { { struct device *dev = &global_pdev->dev; struct cpufreq_qcom *c; struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; struct resource *res; struct resource *res; struct device *dev = &pdev->dev; const u16 *offsets; int ret, i, cpu_r; void __iomem *base; void __iomem *base; int ret, index; cpu_dev = get_cpu_device(policy->cpu); if (qcom_freq_domain_map[cpu]) if (!cpu_dev) { return 0; pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); return -ENODEV; } cpu_np = of_cpu_device_node_get(policy->cpu); if (!cpu_np) return -EINVAL; ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", "#freq-domain-cells", 0, &args); of_node_put(cpu_np); if (ret) return ret; index = args.args[0]; res = platform_get_resource(global_pdev, IORESOURCE_MEM, index); if (!res) return -ENODEV; base = devm_ioremap(dev, res->start, resource_size(res)); c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); if (!base) if (!c) return -ENOMEM; return -ENOMEM; offsets = of_device_get_match_data(dev); offsets = of_device_get_match_data(&pdev->dev); if (!offsets) if (!offsets) return -EINVAL; return -EINVAL; res = platform_get_resource(pdev, IORESOURCE_MEM, index); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) return PTR_ERR(base); for (i = REG_ENABLE; i < REG_ARRAY_SIZE; i++) c->reg_bases[i] = base + offsets[i]; if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) { if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) { /* HW should be in enabled state to proceed */ /* HW should be in enabled state to proceed */ if (!(readl_relaxed(base + offsets[REG_ENABLE]) & 0x1)) { if (!(readl_relaxed(c->reg_bases[REG_ENABLE]) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); index); return -ENODEV; return -ENODEV; } } } } qcom_get_related_cpus(index, policy->cpus); ret = qcom_get_related_cpus(index, &c->related_cpus); if (!cpumask_weight(policy->cpus)) { if (ret) { dev_err(dev, "Domain-%d failed to get related CPUs\n", index); dev_err(dev, "Domain-%d failed to get related CPUs\n", index); ret = -ENOENT; return ret; goto error; } } policy->driver_data = base; c->max_cores = max_cores; if (!c->max_cores) return -ENOENT; ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, args.args[1]); c->xo_rate = xo_rate; c->cpu_hw_rate = cpu_hw_rate; ret = qcom_cpufreq_hw_read_lut(pdev, c); if (ret) { if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); dev_err(dev, "Domain-%d failed to read LUT\n", index); goto error; } ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) { dev_err(cpu_dev, "Failed to add OPPs\n"); ret = -ENODEV; goto error; } dev_pm_opp_of_register_em(policy->cpus); policy->fast_switch_possible = true; policy->dvfs_possible_from_any_cpu = true; return 0; error: devm_iounmap(dev, base); return ret; return ret; } } static void qcom_cpufreq_ready(struct cpufreq_policy *policy) for_each_cpu(cpu_r, &c->related_cpus) { qcom_freq_domain_map[cpu_r] = c; static struct thermal_cooling_device *cdev[NR_CPUS]; struct device_node *np; unsigned int cpu = policy->cpu; if (cdev[cpu]) return; np = of_cpu_device_node_get(cpu); if (WARN_ON(!np)) return; /* * For now, just loading the cooling device; * thermal DT code takes care of matching them. */ if (of_find_property(np, "#cooling-cells", NULL)) { cdev[cpu] = of_cpufreq_cooling_register(policy); if (IS_ERR(cdev[cpu])) { pr_err("running cpufreq for CPU%d without cooling dev: %ld\n", cpu, PTR_ERR(cdev[cpu])); cdev[cpu] = NULL; } } of_node_put(np); } static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { struct device *cpu_dev = get_cpu_device(policy->cpu); void __iomem *base = policy->driver_data; dev_pm_opp_remove_all_dynamic(cpu_dev); kfree(policy->freq_table); devm_iounmap(&global_pdev->dev, base); return 0; return 0; } } static struct freq_attr *qcom_cpufreq_hw_attr[] = { static int qcom_resources_init(struct platform_device *pdev) &cpufreq_freq_attr_scaling_available_freqs, &cpufreq_freq_attr_scaling_boost_freqs, NULL }; static struct cpufreq_driver cpufreq_qcom_hw_driver = { .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, .verify = cpufreq_generic_frequency_table_verify, .target_index = qcom_cpufreq_hw_target_index, .get = qcom_cpufreq_hw_get, .init = qcom_cpufreq_hw_cpu_init, .exit = qcom_cpufreq_hw_cpu_exit, .fast_switch = qcom_cpufreq_hw_fast_switch, .name = "qcom-cpufreq-hw", .attr = qcom_cpufreq_hw_attr, .boost_enabled = true, .ready = qcom_cpufreq_ready, }; static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { { struct cpu_cycle_counter_cb cycle_counter_cb = { struct device_node *cpu_np; .get_cpu_cycle_counter = qcom_cpufreq_get_cpu_cycle_counter, struct of_phandle_args args; }; struct clk *clk; struct clk *clk; unsigned int cpu; unsigned long xo_rate, cpu_hw_rate; int ret; int ret; clk = clk_get(&pdev->dev, "xo"); clk = devm_clk_get(&pdev->dev, "xo"); if (IS_ERR(clk)) if (IS_ERR(clk)) return PTR_ERR(clk); return PTR_ERR(clk); xo_rate = clk_get_rate(clk); xo_rate = clk_get_rate(clk); clk_put(clk); clk = clk_get(&pdev->dev, "alternate"); devm_clk_put(&pdev->dev, clk); clk = devm_clk_get(&pdev->dev, "alternate"); if (IS_ERR(clk)) if (IS_ERR(clk)) return PTR_ERR(clk); return PTR_ERR(clk); cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; clk_put(clk); devm_clk_put(&pdev->dev, clk); of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size", of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size", &lut_row_size); &lut_row_size); global_pdev = pdev; for_each_possible_cpu(cpu) { cpu_np = of_cpu_device_node_get(cpu); if (!cpu_np) { dev_dbg(&pdev->dev, "Failed to get cpu %d device\n", cpu); continue; } ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", if (ret) { "#freq-domain-cells", 0, &args); dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); if (ret < 0) return ret; return ret; } ret = register_cpu_cycle_counter_cb(&cycle_counter_cb); ret = qcom_cpu_resources_init(pdev, cpu, args.args[0], if (ret) { args.args[1], xo_rate, dev_err(&pdev->dev, "cycle counter cb failed to register\n"); cpu_hw_rate); if (ret) return ret; return ret; } } of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); return 0; dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); return ret; } } static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { { return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); int rc; struct cpu_cycle_counter_cb cycle_counter_cb = { .get_cpu_cycle_counter = qcom_cpufreq_get_cpu_cycle_counter, }; /* Get the bases of cpufreq for domains */ rc = qcom_resources_init(pdev); if (rc) { dev_err(&pdev->dev, "CPUFreq resource init failed\n"); return rc; } rc = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (rc) { dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); return rc; } rc = register_cpu_cycle_counter_cb(&cycle_counter_cb); if (rc) { dev_err(&pdev->dev, "cycle counter cb failed to register\n"); return rc; } dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); return 0; } } static const struct of_device_id qcom_cpufreq_hw_match[] = { static const struct of_device_id qcom_cpufreq_hw_match[] = { Loading @@ -440,11 +474,9 @@ static const struct of_device_id qcom_cpufreq_hw_match[] = { .data = &cpufreq_qcom_epss_std_offsets }, .data = &cpufreq_qcom_epss_std_offsets }, {} {} }; }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); static struct platform_driver qcom_cpufreq_hw_driver = { static struct platform_driver qcom_cpufreq_hw_driver = { .probe = qcom_cpufreq_hw_driver_probe, .probe = qcom_cpufreq_hw_driver_probe, .remove = qcom_cpufreq_hw_driver_remove, .driver = { .driver = { .name = "qcom-cpufreq-hw", .name = "qcom-cpufreq-hw", .of_match_table = qcom_cpufreq_hw_match, .of_match_table = qcom_cpufreq_hw_match, Loading @@ -457,11 +489,4 @@ static int __init qcom_cpufreq_hw_init(void) } } subsys_initcall(qcom_cpufreq_hw_init); subsys_initcall(qcom_cpufreq_hw_init); static void __exit qcom_cpufreq_hw_exit(void) MODULE_DESCRIPTION("QCOM firmware-based CPU Frequency driver"); { platform_driver_unregister(&qcom_cpufreq_hw_driver); } module_exit(qcom_cpufreq_hw_exit); MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); MODULE_LICENSE("GPL v2");
