Commit d92f842b authored Sep 20, 2017 by Scott Tsai Committed by Paul E. McKenney Oct 20, 2017

memory-barriers.txt: Fix typo in pairing example



In the "general barrier pairing with implicit control depdendency"
example, the last write by CPU 1 was meant to change variable x and not
y. The example would be pretty uninteresting if no CPU ever changes x
and the variable was initialized to zero.

Signed-off-by: Scott Tsai <scottt@scottt.tw>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>

parent 0902b1f4

Documentation/memory-barriers.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -947,7 +947,7 @@ Or even:
		=============== ===============================
		r1 = READ_ONCE(y);
		<general barrier>
		WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
		WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
		<implicit control dependency>
		WRITE_ONCE(y, 1);
		}