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Commit d696db77 authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Tharun Raj Soma
Browse files

drm/msm/dsi-staging: add support for overlap pixels in dsi driver 



In foldable phones, panels show extra overlap pixels data per dsi.
Due to which the effective width of the panel per dsi becomes
actual width in pixels plus size of overlap pixels. This change
adds support in dsi driver for overlap pixels used in foldable phones.

Change-Id: Ic9dbf3db9fe3e301fa12c198c6d34ce2de08b5e8
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
Signed-off-by: default avatarTharun Raj Soma <tsoma@codeaurora.org>
parent ab872dd5

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+2 −0
Original line number Diff line number Diff line
@@ -143,6 +143,8 @@ Optional properties: 
					0 = default value

- qcom,mdss-dsi-v-bottom-border:	Vertical bottom border in pixel.

					0 = default value

- qcom,mdss-dsi-overlap-pixels:		Horizontal overlap pixels for certain panels.

					0 = default value

- qcom,mdss-dsi-underflow-color:	Specifies the controller settings for the

					panel under flow color.

					0xff = default value.

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+6 −3
Original line number Diff line number Diff line
@@ -843,6 +843,7 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	if (config->bit_clk_rate_hz_override == 0) {

		if (config->panel_mode == DSI_OP_CMD_MODE) {

			h_period = DSI_H_ACTIVE_DSC(timing);

			h_period += timing->overlap_pixels;

			v_period = timing->v_active;



			do_div(refresh_rate, timing->mdp_transfer_time_us);
@@ -2929,10 +2930,12 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl, 


	pr_debug("[DSI_%d]Host config updated\n", ctrl->cell_index);

	memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config));

	ctrl->mode_bounds.x = ctrl->host_config.video_timing.h_active *

	ctrl->mode_bounds.x = (ctrl->host_config.video_timing.h_active +

			ctrl->host_config.video_timing.overlap_pixels) *

						 ctrl->horiz_index;

	ctrl->mode_bounds.y = 0;

	ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active;

	ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active +

				ctrl->host_config.video_timing.overlap_pixels;

	ctrl->mode_bounds.h = ctrl->host_config.video_timing.v_active;

	memcpy(&ctrl->roi, &ctrl->mode_bounds, sizeof(ctrl->mode_bounds));

	ctrl->modeupdated = true;

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+3 −3
Original line number Diff line number Diff line
@@ -310,7 +310,7 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, 
		reg |= 1;

		DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);

	} else {

		width = mode->h_active;

		width = mode->h_active + mode->overlap_pixels;

	}



	hs_end = mode->h_sync_width;
@@ -421,8 +421,8 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, 
		stride_final = roi->w * 3;

		height_final = roi->h;

	} else {

		width_final = mode->h_active;

		stride_final = h_stride;

		width_final = mode->h_active + mode->overlap_pixels;

		stride_final = h_stride + mode->overlap_pixels * 3;

		height_final = mode->v_active;

	}

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+4 −0
Original line number Diff line number Diff line
@@ -389,6 +389,7 @@ struct dsi_panel_cmd_set { 
 * @clk_rate_hz:      DSI bit clock rate per lane in Hz.

 * @mdp_transfer_time_us:   Specifies the mdp transfer time for command mode

 *                    panels in microseconds.

 * @overlap_pixels:   overlap pixels for certain panels.

 * @dsc_enabled:      DSC compression enabled.

 * @dsc:              DSC compression configuration.

 * @roi_caps:         Panel ROI capabilities.
@@ -410,6 +411,7 @@ struct dsi_mode_info { 
	u32 refresh_rate;

	u64 clk_rate_hz;

	u32 mdp_transfer_time_us;

	u32 overlap_pixels;

	bool dsc_enabled;

	struct msm_display_dsc_info *dsc;

	struct msm_roi_caps roi_caps;
@@ -560,6 +562,7 @@ struct dsi_host_config { 
 * @mdp_transfer_time_us:   Specifies the mdp transfer time for command mode

 *                          panels in microseconds.

 * @clk_rate_hz:          DSI bit clock per lane in hz.

 * @overlap_pixels:       overlap pixels for certain panels.

 * @topology:             Topology selected for the panel

 * @dsc:                  DSC compression info

 * @dsc_enabled:          DSC compression enabled
@@ -576,6 +579,7 @@ struct dsi_display_mode_priv_info { 
	u32 panel_prefill_lines;

	u32 mdp_transfer_time_us;

	u64 clk_rate_hz;

	u32 overlap_pixels;



	struct msm_display_topology topology;

	struct msm_display_dsc_info dsc;

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+7 −1
Original line number Diff line number Diff line
@@ -4302,6 +4302,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, 
	struct dsi_display_mode per_ctrl_mode;

	struct dsi_mode_info *timing;

	struct dsi_ctrl *m_ctrl;

	u32 overlap_pixels = 0;



	int rc = 0;
@@ -4336,6 +4337,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, 
	}

	/* TODO: Remove this direct reference to the dsi_ctrl */

	timing = &per_ctrl_mode.timing;

	overlap_pixels = per_ctrl_mode.priv_info->overlap_pixels;



	switch (dfps_caps.type) {

	case DSI_DFPS_IMMEDIATE_VFP:
@@ -4353,7 +4355,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, 
				curr_refresh_rate,

				timing->refresh_rate,

				DSI_V_TOTAL(timing),

				DSI_H_TOTAL_DSC(timing),

				DSI_H_TOTAL_DSC(timing) + overlap_pixels,

				timing->h_front_porch,

				&adj_mode->timing.h_front_porch);

		if (!rc)
@@ -6153,6 +6155,10 @@ int dsi_display_get_modes(struct dsi_display *display, 
			panel_mode.pixel_clk_khz *= display->ctrl_count;

		}



		/* pixel overlap is not supported for single dsi panels */

		if (display->ctrl_count == 1)

			panel_mode.priv_info->overlap_pixels = 0;



		start = array_idx;



		for (i = 0; i < num_dfps_rates; i++) {