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Commit d5ea1177 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: clk-rcg2: Clear the HW_CLK_CONTROL bit of the RCG 



For some clock sources, the HW clock control is enabled
by default. This feature is not used by software. Hence
disable it.

Change-Id: I5db4141f20824d6d9ed0655b7f823ed770da90bc
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 02acb402

drivers/clk/qcom/clk-rcg2.c

+2 −1
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#define CFG_MODE_SHIFT		12

#define CFG_MODE_MASK		(0x3 << CFG_MODE_SHIFT)

#define CFG_MODE_DUAL_EDGE	(0x2 << CFG_MODE_SHIFT)

#define CFG_HW_CLK_CTRL_MASK	BIT(20)



#define M_REG			0x8

#define N_REG			0xc
@@ -396,7 +397,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 
	}



	mask = BIT(rcg->hid_width) - 1;

	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;

	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;

	cfg = f->pre_div << CFG_SRC_DIV_SHIFT;

	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;

	if (rcg->mnd_width && f->n && (f->m != f->n))