Loading drivers/gpu/drm/nouveau/include/nvif/class.h +3 −0 Original line number Diff line number Diff line Loading @@ -155,6 +155,8 @@ #define PASCAL_A /* cl9097.h */ 0x0000c097 #define PASCAL_B /* cl9097.h */ 0x0000c197 #define VOLTA_A /* cl9097.h */ 0x0000c397 #define NV74_BSP 0x000074b0 #define GT212_MSVLD 0x000085b1 Loading Loading @@ -194,6 +196,7 @@ #define MAXWELL_COMPUTE_B 0x0000b1c0 #define PASCAL_COMPUTE_A 0x0000c0c0 #define PASCAL_COMPUTE_B 0x0000c1c0 #define VOLTA_COMPUTE_A 0x0000c3c0 #define NV74_CIPHER 0x000074c1 #endif drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +1 −0 Original line number Diff line number Diff line Loading @@ -48,4 +48,5 @@ int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); #endif drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +4 −0 Original line number Diff line number Diff line Loading @@ -2413,6 +2413,7 @@ nv140_chipset = { .mmu = gv100_mmu_new, .pci = gp100_pci_new, .pmu = gp102_pmu_new, .secboot = gp108_secboot_new, .therm = gp100_therm_new, .timer = gk20a_timer_new, .top = gk104_top_new, Loading @@ -2428,6 +2429,9 @@ nv140_chipset = { .ce[8] = gv100_ce_new, .dma = gv100_dma_new, .fifo = gv100_fifo_new, .gr = gv100_gr_new, .nvdec = gp102_nvdec_new, .sec2 = gp102_sec2_new, }; static int Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +2 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ nvkm-y += nvkm/engine/gr/gp102.o nvkm-y += nvkm/engine/gr/gp104.o nvkm-y += nvkm/engine/gr/gp107.o nvkm-y += nvkm/engine/gr/gp10b.o nvkm-y += nvkm/engine/gr/gv100.o nvkm-y += nvkm/engine/gr/ctxnv40.o nvkm-y += nvkm/engine/gr/ctxnv50.o Loading @@ -57,3 +58,4 @@ nvkm-y += nvkm/engine/gr/ctxgp100.o nvkm-y += nvkm/engine/gr/ctxgp102.o nvkm-y += nvkm/engine/gr/ctxgp104.o nvkm-y += nvkm/engine/gr/ctxgp107.o nvkm-y += nvkm/engine/gr/ctxgv100.o drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +10 −0 Original line number Diff line number Diff line Loading @@ -1396,10 +1396,14 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_floorsweep(gr); if (grctx->r400088) grctx->r400088(gr, false); if (gr->fuc_bundle) gf100_gr_icmd(gr, gr->fuc_bundle); else gf100_gr_icmd(gr, grctx->icmd); if (grctx->sw_veid_bundle_init) gf100_gr_icmd(gr, grctx->sw_veid_bundle_init); if (grctx->r400088) grctx->r400088(gr, true); nvkm_wr32(device, 0x404154, idle_timeout); Loading Loading @@ -1448,6 +1452,9 @@ gf100_grctx_generate(struct gf100_gr *gr) break; ); if (grctx->unkn88c) grctx->unkn88c(gr, true); /* Reset FECS. */ nvkm_wr32(device, 0x409614, 0x00000070); nvkm_usec(device, 10, NVKM_DELAY); Loading @@ -1455,6 +1462,9 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_usec(device, 10, NVKM_DELAY); nvkm_rd32(device, 0x409614); if (grctx->unkn88c) grctx->unkn88c(gr, false); /* NV_PGRAPH_FE_PWR_MODE_AUTO. */ nvkm_wr32(device, 0x404170, 0x00000010); Loading Loading
drivers/gpu/drm/nouveau/include/nvif/class.h +3 −0 Original line number Diff line number Diff line Loading @@ -155,6 +155,8 @@ #define PASCAL_A /* cl9097.h */ 0x0000c097 #define PASCAL_B /* cl9097.h */ 0x0000c197 #define VOLTA_A /* cl9097.h */ 0x0000c397 #define NV74_BSP 0x000074b0 #define GT212_MSVLD 0x000085b1 Loading Loading @@ -194,6 +196,7 @@ #define MAXWELL_COMPUTE_B 0x0000b1c0 #define PASCAL_COMPUTE_A 0x0000c0c0 #define PASCAL_COMPUTE_B 0x0000c1c0 #define VOLTA_COMPUTE_A 0x0000c3c0 #define NV74_CIPHER 0x000074c1 #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +1 −0 Original line number Diff line number Diff line Loading @@ -48,4 +48,5 @@ int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); #endif
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +4 −0 Original line number Diff line number Diff line Loading @@ -2413,6 +2413,7 @@ nv140_chipset = { .mmu = gv100_mmu_new, .pci = gp100_pci_new, .pmu = gp102_pmu_new, .secboot = gp108_secboot_new, .therm = gp100_therm_new, .timer = gk20a_timer_new, .top = gk104_top_new, Loading @@ -2428,6 +2429,9 @@ nv140_chipset = { .ce[8] = gv100_ce_new, .dma = gv100_dma_new, .fifo = gv100_fifo_new, .gr = gv100_gr_new, .nvdec = gp102_nvdec_new, .sec2 = gp102_sec2_new, }; static int Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +2 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ nvkm-y += nvkm/engine/gr/gp102.o nvkm-y += nvkm/engine/gr/gp104.o nvkm-y += nvkm/engine/gr/gp107.o nvkm-y += nvkm/engine/gr/gp10b.o nvkm-y += nvkm/engine/gr/gv100.o nvkm-y += nvkm/engine/gr/ctxnv40.o nvkm-y += nvkm/engine/gr/ctxnv50.o Loading @@ -57,3 +58,4 @@ nvkm-y += nvkm/engine/gr/ctxgp100.o nvkm-y += nvkm/engine/gr/ctxgp102.o nvkm-y += nvkm/engine/gr/ctxgp104.o nvkm-y += nvkm/engine/gr/ctxgp107.o nvkm-y += nvkm/engine/gr/ctxgv100.o
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +10 −0 Original line number Diff line number Diff line Loading @@ -1396,10 +1396,14 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_floorsweep(gr); if (grctx->r400088) grctx->r400088(gr, false); if (gr->fuc_bundle) gf100_gr_icmd(gr, gr->fuc_bundle); else gf100_gr_icmd(gr, grctx->icmd); if (grctx->sw_veid_bundle_init) gf100_gr_icmd(gr, grctx->sw_veid_bundle_init); if (grctx->r400088) grctx->r400088(gr, true); nvkm_wr32(device, 0x404154, idle_timeout); Loading Loading @@ -1448,6 +1452,9 @@ gf100_grctx_generate(struct gf100_gr *gr) break; ); if (grctx->unkn88c) grctx->unkn88c(gr, true); /* Reset FECS. */ nvkm_wr32(device, 0x409614, 0x00000070); nvkm_usec(device, 10, NVKM_DELAY); Loading @@ -1455,6 +1462,9 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_usec(device, 10, NVKM_DELAY); nvkm_rd32(device, 0x409614); if (grctx->unkn88c) grctx->unkn88c(gr, false); /* NV_PGRAPH_FE_PWR_MODE_AUTO. */ nvkm_wr32(device, 0x404170, 0x00000010); Loading