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Commit d43af505 authored by Jakub Kicinski's avatar Jakub Kicinski Committed by Kalle Valo
Browse files

mt7601u: use linux/bitfield.h 



Use the newly added linux/bitfield.h.

Signed-off-by: default avatarJakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: default avatarDinan Gunawardena <dinan.gunawardena@netronome.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent adcc710d

drivers/net/wireless/mediatek/mt7601u/dma.c

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static void mt7601u_rx_process_seg(struct mt7601u_dev *dev, u8 *data, 


	if (unlikely(rxwi->zero[0] || rxwi->zero[1] || rxwi->zero[2]))

		dev_err_once(dev->dev, "Error: RXWI zero fields are set\n");

	if (unlikely(MT76_GET(MT_RXD_INFO_TYPE, fce_info)))

	if (unlikely(FIELD_GET(MT_RXD_INFO_TYPE, fce_info)))

		dev_err_once(dev->dev, "Error: RX path seen a non-pkt urb\n");



	trace_mt_rx(dev, rxwi, fce_info);

drivers/net/wireless/mediatek/mt7601u/dma.h

+4 −6
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 
#include <asm/unaligned.h>

#include <linux/skbuff.h>



#include "util.h"



#define MT_DMA_HDR_LEN			4

#define MT_RX_INFO_LEN			4

#define MT_FCE_INFO_LEN			4
@@ -79,9 +77,9 @@ static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb, 
	 */



	info = flags |

		MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |

		MT76_SET(MT_TXD_INFO_D_PORT, d_port) |

		MT76_SET(MT_TXD_INFO_TYPE, type);

		FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |

		FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) |

		FIELD_PREP(MT_TXD_INFO_TYPE, type);



	put_unaligned_le32(info, skb_push(skb, sizeof(info)));

	return skb_put_padto(skb, round_up(skb->len, 4) + 4);
@@ -90,7 +88,7 @@ static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb, 
static inline int

mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)

{

	flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel);

	flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel);

	return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);

}

drivers/net/wireless/mediatek/mt7601u/eeprom.c

+6 −6
Original line number Diff line number Diff line
@@ -45,8 +45,8 @@ mt7601u_efuse_read(struct mt7601u_dev *dev, u16 addr, u8 *data, 
	val = mt76_rr(dev, MT_EFUSE_CTRL);

	val &= ~(MT_EFUSE_CTRL_AIN |

		 MT_EFUSE_CTRL_MODE);

	val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf) |

	       MT76_SET(MT_EFUSE_CTRL_MODE, mode) |

	val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf) |

	       FIELD_PREP(MT_EFUSE_CTRL_MODE, mode) |

	       MT_EFUSE_CTRL_KICK;

	mt76_wr(dev, MT_EFUSE_CTRL, val);
@@ -128,8 +128,8 @@ mt7601u_set_chip_cap(struct mt7601u_dev *dev, u8 *eeprom) 
	if (!field_valid(nic_conf0 >> 8))

		return;



	if (MT76_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||

	    MT76_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)

	if (FIELD_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||

	    FIELD_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)

		dev_err(dev->dev,

			"Error: device has more than 1 RX/TX stream!\n");

}
@@ -150,7 +150,7 @@ mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *eeprom) 


	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));

	mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) |

		MT76_SET(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));

		FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));



	return 0;

}
@@ -176,7 +176,7 @@ mt7601u_set_channel_power(struct mt7601u_dev *dev, u8 *eeprom) 
	u8 max_pwr;



	val = mt7601u_rr(dev, MT_TX_ALC_CFG_0);

	max_pwr = MT76_GET(MT_TX_ALC_CFG_0_LIMIT_0, val);

	max_pwr = FIELD_GET(MT_TX_ALC_CFG_0_LIMIT_0, val);



	if (mt7601u_has_tssi(dev, eeprom)) {

		mt7601u_set_channel_target_power(dev, eeprom, max_pwr);

drivers/net/wireless/mediatek/mt7601u/init.c

+6 −4
Original line number Diff line number Diff line
@@ -108,8 +108,9 @@ static void mt7601u_init_usb_dma(struct mt7601u_dev *dev) 
{

	u32 val;



	val = MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |

	      MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) |

	val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |

	      FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT,

			 MT_USB_AGGR_SIZE_LIMIT) |

	      MT_USB_DMA_CFG_RX_BULK_EN |

	      MT_USB_DMA_CFG_TX_BULK_EN;

	if (dev->in_max_packet == 512)
@@ -396,8 +397,9 @@ int mt7601u_init_hardware(struct mt7601u_dev *dev) 


	mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);



	mt7601u_wr(dev, MT_TXOP_CTRL_CFG, MT76_SET(MT_TXOP_TRUN_EN, 0x3f) |

					  MT76_SET(MT_TXOP_EXT_CCA_DLY, 0x58));

	mt7601u_wr(dev, MT_TXOP_CTRL_CFG,

		   FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |

		   FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));



	ret = mt7601u_eeprom_init(dev);

	if (ret)

drivers/net/wireless/mediatek/mt7601u/mac.c

+19 −19
Original line number Diff line number Diff line
@@ -19,13 +19,13 @@ 
static void

mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate)

{

	u8 idx = MT76_GET(MT_TXWI_RATE_MCS, rate);

	u8 idx = FIELD_GET(MT_TXWI_RATE_MCS, rate);



	txrate->idx = 0;

	txrate->flags = 0;

	txrate->count = 1;



	switch (MT76_GET(MT_TXWI_RATE_PHY_MODE, rate)) {

	switch (FIELD_GET(MT_TXWI_RATE_PHY_MODE, rate)) {

	case MT_PHY_TYPE_OFDM:

		txrate->idx = idx + 4;

		return;
@@ -47,7 +47,7 @@ mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate) 
		return;

	}



	if (MT76_GET(MT_TXWI_RATE_BW, rate) == MT_PHY_BW_40)

	if (FIELD_GET(MT_TXWI_RATE_BW, rate) == MT_PHY_BW_40)

		txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;



	if (rate & MT_TXWI_RATE_SGI)
@@ -125,9 +125,9 @@ u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, 
		bw = 0;

	}



	rateval = MT76_SET(MT_RXWI_RATE_MCS, rate_idx);

	rateval |= MT76_SET(MT_RXWI_RATE_PHY, phy);

	rateval |= MT76_SET(MT_RXWI_RATE_BW, bw);

	rateval = FIELD_PREP(MT_RXWI_RATE_MCS, rate_idx);

	rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);

	rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);

	if (rate->flags & IEEE80211_TX_RC_SHORT_GI)

		rateval |= MT_RXWI_RATE_SGI;
@@ -156,9 +156,9 @@ struct mt76_tx_status mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev) 
	stat.success = !!(val & MT_TX_STAT_FIFO_SUCCESS);

	stat.aggr = !!(val & MT_TX_STAT_FIFO_AGGR);

	stat.ack_req = !!(val & MT_TX_STAT_FIFO_ACKREQ);

	stat.pktid = MT76_GET(MT_TX_STAT_FIFO_PID_TYPE, val);

	stat.wcid = MT76_GET(MT_TX_STAT_FIFO_WCID, val);

	stat.rate = MT76_GET(MT_TX_STAT_FIFO_RATE, val);

	stat.pktid = FIELD_GET(MT_TX_STAT_FIFO_PID_TYPE, val);

	stat.wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, val);

	stat.rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, val);



	return stat;

}
@@ -270,7 +270,7 @@ void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval) 
	}



	val &= ~MT_BEACON_TIME_CFG_INTVAL;

	val |= MT76_SET(MT_BEACON_TIME_CFG_INTVAL, interval << 4) |

	val |= FIELD_PREP(MT_BEACON_TIME_CFG_INTVAL, interval << 4) |

		MT_BEACON_TIME_CFG_TIMER_EN |

		MT_BEACON_TIME_CFG_SYNC_MODE |

		MT_BEACON_TIME_CFG_TBTT_EN;
@@ -349,8 +349,8 @@ mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac) 
	u8 zmac[ETH_ALEN] = {};

	u32 attr;



	attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |

	       MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));

	attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |

	       FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));



	mt76_wr(dev, MT_WCID_ATTR(idx), attr);
@@ -382,15 +382,15 @@ void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev) 
	rcu_read_unlock();



	mt7601u_wr(dev, MT_MAX_LEN_CFG, 0xa0fff |

		   MT76_SET(MT_MAX_LEN_CFG_AMPDU, min_factor));

		   FIELD_PREP(MT_MAX_LEN_CFG_AMPDU, min_factor));

}



static void

mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)

{

	u8 idx = MT76_GET(MT_RXWI_RATE_MCS, rate);

	u8 idx = FIELD_GET(MT_RXWI_RATE_MCS, rate);



	switch (MT76_GET(MT_RXWI_RATE_PHY, rate)) {

	switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {

	case MT_PHY_TYPE_OFDM:

		if (WARN_ON(idx >= 8))

			idx = 0;
@@ -436,7 +436,7 @@ mt7601u_rx_monitor_beacon(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, 
			  u16 rate, int rssi)

{

	dev->bcn_freq_off = rxwi->freq_off;

	dev->bcn_phy_mode = MT76_GET(MT_RXWI_RATE_PHY, rate);

	dev->bcn_phy_mode = FIELD_GET(MT_RXWI_RATE_PHY, rate);

	dev->avg_rssi = (dev->avg_rssi * 15) / 16 + (rssi << 8);

}
@@ -458,7 +458,7 @@ u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, 
	u16 rate = le16_to_cpu(rxwi->rate);

	int rssi;



	len = MT76_GET(MT_RXWI_CTL_MPDU_LEN, ctl);

	len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl);

	if (len < 10)

		return 0;
@@ -542,8 +542,8 @@ int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, 


	val = mt7601u_rr(dev, MT_WCID_ATTR(idx));

	val &= ~MT_WCID_ATTR_PKEY_MODE & ~MT_WCID_ATTR_PKEY_MODE_EXT;

	val |= MT76_SET(MT_WCID_ATTR_PKEY_MODE, cipher & 7) |

	       MT76_SET(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3);

	val |= FIELD_PREP(MT_WCID_ATTR_PKEY_MODE, cipher & 7) |

	       FIELD_PREP(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3);

	val &= ~MT_WCID_ATTR_PAIRWISE;

	val |= MT_WCID_ATTR_PAIRWISE *

		!!(key && key->flags & IEEE80211_KEY_FLAG_PAIRWISE);