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Commit d2d2e54d authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: imx6qdl: switch to use macro for clock ID 



Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro.  In this case, device tree can reuse these macros to improve
readability.

Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent a25d67a4

Documentation/devicetree/bindings/clock/imx6q-clock.txt

+5 −215
Original line number Original line Diff line number Diff line
@@ -7,223 +7,13 @@ Required properties: 
- #clock-cells: Should be <1>

- #clock-cells: Should be <1>





The clock consumer should specify the desired clock by having the clock

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6qdl-clock.h

clocks and IDs.

for the full list of i.MX6 Quad and DualLite clock IDs.



	Clock			ID

	---------------------------

	dummy			0

	ckil			1

	ckih			2

	osc			3

	pll2_pfd0_352m		4

	pll2_pfd1_594m		5

	pll2_pfd2_396m		6

	pll3_pfd0_720m		7

	pll3_pfd1_540m		8

	pll3_pfd2_508m		9

	pll3_pfd3_454m		10

	pll2_198m		11

	pll3_120m		12

	pll3_80m		13

	pll3_60m		14

	twd			15

	step			16

	pll1_sw			17

	periph_pre		18

	periph2_pre		19

	periph_clk2_sel		20

	periph2_clk2_sel	21

	axi_sel			22

	esai_sel		23

	asrc_sel		24

	spdif_sel		25

	gpu2d_axi		26

	gpu3d_axi		27

	gpu2d_core_sel		28

	gpu3d_core_sel		29

	gpu3d_shader_sel	30

	ipu1_sel		31

	ipu2_sel		32

	ldb_di0_sel		33

	ldb_di1_sel		34

	ipu1_di0_pre_sel	35

	ipu1_di1_pre_sel	36

	ipu2_di0_pre_sel	37

	ipu2_di1_pre_sel	38

	ipu1_di0_sel		39

	ipu1_di1_sel		40

	ipu2_di0_sel		41

	ipu2_di1_sel		42

	hsi_tx_sel		43

	pcie_axi_sel		44

	ssi1_sel		45

	ssi2_sel		46

	ssi3_sel		47

	usdhc1_sel		48

	usdhc2_sel		49

	usdhc3_sel		50

	usdhc4_sel		51

	enfc_sel		52

	emi_sel			53

	emi_slow_sel		54

	vdo_axi_sel		55

	vpu_axi_sel		56

	cko1_sel		57

	periph			58

	periph2			59

	periph_clk2		60

	periph2_clk2		61

	ipg			62

	ipg_per			63

	esai_pred		64

	esai_podf		65

	asrc_pred		66

	asrc_podf		67

	spdif_pred		68

	spdif_podf		69

	can_root		70

	ecspi_root		71

	gpu2d_core_podf		72

	gpu3d_core_podf		73

	gpu3d_shader		74

	ipu1_podf		75

	ipu2_podf		76

	ldb_di0_podf		77

	ldb_di1_podf		78

	ipu1_di0_pre		79

	ipu1_di1_pre		80

	ipu2_di0_pre		81

	ipu2_di1_pre		82

	hsi_tx_podf		83

	ssi1_pred		84

	ssi1_podf		85

	ssi2_pred		86

	ssi2_podf		87

	ssi3_pred		88

	ssi3_podf		89

	uart_serial_podf	90

	usdhc1_podf		91

	usdhc2_podf		92

	usdhc3_podf		93

	usdhc4_podf		94

	enfc_pred		95

	enfc_podf		96

	emi_podf		97

	emi_slow_podf		98

	vpu_axi_podf		99

	cko1_podf		100

	axi			101

	mmdc_ch0_axi_podf	102

	mmdc_ch1_axi_podf	103

	arm			104

	ahb			105

	apbh_dma		106

	asrc			107

	can1_ipg		108

	can1_serial		109

	can2_ipg		110

	can2_serial		111

	ecspi1			112

	ecspi2			113

	ecspi3			114

	ecspi4			115

	ecspi5			116

	enet			117

	esai			118

	gpt_ipg			119

	gpt_ipg_per		120

	gpu2d_core		121

	gpu3d_core		122

	hdmi_iahb		123

	hdmi_isfr		124

	i2c1			125

	i2c2			126

	i2c3			127

	iim			128

	enfc			129

	ipu1			130

	ipu1_di0		131

	ipu1_di1		132

	ipu2			133

	ipu2_di0		134

	ldb_di0			135

	ldb_di1			136

	ipu2_di1		137

	hsi_tx			138

	mlb			139

	mmdc_ch0_axi		140

	mmdc_ch1_axi		141

	ocram			142

	openvg_axi		143

	pcie_axi		144

	pwm1			145

	pwm2			146

	pwm3			147

	pwm4			148

	per1_bch		149

	gpmi_bch_apb		150

	gpmi_bch		151

	gpmi_io			152

	gpmi_apb		153

	sata			154

	sdma			155

	spba			156

	ssi1			157

	ssi2			158

	ssi3			159

	uart_ipg		160

	uart_serial		161

	usboh3			162

	usdhc1			163

	usdhc2			164

	usdhc3			165

	usdhc4			166

	vdo_axi			167

	vpu_axi			168

	cko1			169

	pll1_sys		170

	pll2_bus		171

	pll3_usb_otg		172

	pll4_audio		173

	pll5_video		174

	pll8_mlb		175

	pll7_usb_host		176

	pll6_enet		177

	ssi1_ipg		178

	ssi2_ipg		179

	ssi3_ipg		180

	rom			181

	usbphy1			182

	usbphy2			183

	ldb_di0_div_3_5		184

	ldb_di1_div_3_5		185

	sata_ref		186

	sata_ref_100m		187

	pcie_ref		188

	pcie_ref_125m		189

	enet_ref		190

	usbphy1_gate		191

	usbphy2_gate		192

	pll4_post_div		193

	pll5_post_div		194

	pll5_video_div		195

	eim_slow      		196

	spdif      		197

	cko2_sel      		198

	cko2_podf      		199

	cko2      		200

	cko      		201

	vdoa      		202

	pll4_audio_div		203

	lvds1_sel		204

	lvds2_sel		205

	lvds1_gate		206

	lvds2_gate		207

	esai_ahb		208





Examples:

Examples:





#include <dt-bindings/clock/imx6qdl-clock.h>



clks: ccm@020c4000 {

clks: ccm@020c4000 {

	compatible = "fsl,imx6q-ccm";

	compatible = "fsl,imx6q-ccm";

	reg = <0x020c4000 0x4000>;

	reg = <0x020c4000 0x4000>;
@@ -235,7 +25,7 @@ uart1: serial@02020000 { 
	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

	reg = <0x02020000 0x4000>;

	reg = <0x02020000 0x4000>;

	interrupts = <0 26 0x04>;

	interrupts = <0 26 0x04>;

	clocks = <&clks 160>, <&clks 161>;

	clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;

	clock-names = "ipg", "per";

	clock-names = "ipg", "per";

	status = "disabled";

	status = "disabled";

};
 
};

arch/arm/mach-imx/clk-imx6q.c

+247 −282

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/imx6qdl-clock.h

0 → 100644
+224 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2014 Freescale Semiconductor, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H

#define __DT_BINDINGS_CLOCK_IMX6QDL_H



#define IMX6QDL_CLK_DUMMY			0

#define IMX6QDL_CLK_CKIL			1

#define IMX6QDL_CLK_CKIH			2

#define IMX6QDL_CLK_OSC				3

#define IMX6QDL_CLK_PLL2_PFD0_352M		4

#define IMX6QDL_CLK_PLL2_PFD1_594M		5

#define IMX6QDL_CLK_PLL2_PFD2_396M		6

#define IMX6QDL_CLK_PLL3_PFD0_720M		7

#define IMX6QDL_CLK_PLL3_PFD1_540M		8

#define IMX6QDL_CLK_PLL3_PFD2_508M		9

#define IMX6QDL_CLK_PLL3_PFD3_454M		10

#define IMX6QDL_CLK_PLL2_198M			11

#define IMX6QDL_CLK_PLL3_120M			12

#define IMX6QDL_CLK_PLL3_80M			13

#define IMX6QDL_CLK_PLL3_60M			14

#define IMX6QDL_CLK_TWD				15

#define IMX6QDL_CLK_STEP			16

#define IMX6QDL_CLK_PLL1_SW			17

#define IMX6QDL_CLK_PERIPH_PRE			18

#define IMX6QDL_CLK_PERIPH2_PRE			19

#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20

#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21

#define IMX6QDL_CLK_AXI_SEL			22

#define IMX6QDL_CLK_ESAI_SEL			23

#define IMX6QDL_CLK_ASRC_SEL			24

#define IMX6QDL_CLK_SPDIF_SEL			25

#define IMX6QDL_CLK_GPU2D_AXI			26

#define IMX6QDL_CLK_GPU3D_AXI			27

#define IMX6QDL_CLK_GPU2D_CORE_SEL		28

#define IMX6QDL_CLK_GPU3D_CORE_SEL		29

#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30

#define IMX6QDL_CLK_IPU1_SEL			31

#define IMX6QDL_CLK_IPU2_SEL			32

#define IMX6QDL_CLK_LDB_DI0_SEL			33

#define IMX6QDL_CLK_LDB_DI1_SEL			34

#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35

#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36

#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37

#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38

#define IMX6QDL_CLK_IPU1_DI0_SEL		39

#define IMX6QDL_CLK_IPU1_DI1_SEL		40

#define IMX6QDL_CLK_IPU2_DI0_SEL		41

#define IMX6QDL_CLK_IPU2_DI1_SEL		42

#define IMX6QDL_CLK_HSI_TX_SEL			43

#define IMX6QDL_CLK_PCIE_AXI_SEL		44

#define IMX6QDL_CLK_SSI1_SEL			45

#define IMX6QDL_CLK_SSI2_SEL			46

#define IMX6QDL_CLK_SSI3_SEL			47

#define IMX6QDL_CLK_USDHC1_SEL			48

#define IMX6QDL_CLK_USDHC2_SEL			49

#define IMX6QDL_CLK_USDHC3_SEL			50

#define IMX6QDL_CLK_USDHC4_SEL			51

#define IMX6QDL_CLK_ENFC_SEL			52

#define IMX6QDL_CLK_EMI_SEL			53

#define IMX6QDL_CLK_EMI_SLOW_SEL		54

#define IMX6QDL_CLK_VDO_AXI_SEL			55

#define IMX6QDL_CLK_VPU_AXI_SEL			56

#define IMX6QDL_CLK_CKO1_SEL			57

#define IMX6QDL_CLK_PERIPH			58

#define IMX6QDL_CLK_PERIPH2			59

#define IMX6QDL_CLK_PERIPH_CLK2			60

#define IMX6QDL_CLK_PERIPH2_CLK2		61

#define IMX6QDL_CLK_IPG				62

#define IMX6QDL_CLK_IPG_PER			63

#define IMX6QDL_CLK_ESAI_PRED			64

#define IMX6QDL_CLK_ESAI_PODF			65

#define IMX6QDL_CLK_ASRC_PRED			66

#define IMX6QDL_CLK_ASRC_PODF			67

#define IMX6QDL_CLK_SPDIF_PRED			68

#define IMX6QDL_CLK_SPDIF_PODF			69

#define IMX6QDL_CLK_CAN_ROOT			70

#define IMX6QDL_CLK_ECSPI_ROOT			71

#define IMX6QDL_CLK_GPU2D_CORE_PODF		72

#define IMX6QDL_CLK_GPU3D_CORE_PODF		73

#define IMX6QDL_CLK_GPU3D_SHADER		74

#define IMX6QDL_CLK_IPU1_PODF			75

#define IMX6QDL_CLK_IPU2_PODF			76

#define IMX6QDL_CLK_LDB_DI0_PODF		77

#define IMX6QDL_CLK_LDB_DI1_PODF		78

#define IMX6QDL_CLK_IPU1_DI0_PRE		79

#define IMX6QDL_CLK_IPU1_DI1_PRE		80

#define IMX6QDL_CLK_IPU2_DI0_PRE		81

#define IMX6QDL_CLK_IPU2_DI1_PRE		82

#define IMX6QDL_CLK_HSI_TX_PODF			83

#define IMX6QDL_CLK_SSI1_PRED			84

#define IMX6QDL_CLK_SSI1_PODF			85

#define IMX6QDL_CLK_SSI2_PRED			86

#define IMX6QDL_CLK_SSI2_PODF			87

#define IMX6QDL_CLK_SSI3_PRED			88

#define IMX6QDL_CLK_SSI3_PODF			89

#define IMX6QDL_CLK_UART_SERIAL_PODF		90

#define IMX6QDL_CLK_USDHC1_PODF			91

#define IMX6QDL_CLK_USDHC2_PODF			92

#define IMX6QDL_CLK_USDHC3_PODF			93

#define IMX6QDL_CLK_USDHC4_PODF			94

#define IMX6QDL_CLK_ENFC_PRED			95

#define IMX6QDL_CLK_ENFC_PODF			96

#define IMX6QDL_CLK_EMI_PODF			97

#define IMX6QDL_CLK_EMI_SLOW_PODF		98

#define IMX6QDL_CLK_VPU_AXI_PODF		99

#define IMX6QDL_CLK_CKO1_PODF			100

#define IMX6QDL_CLK_AXI				101

#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102

#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103

#define IMX6QDL_CLK_ARM				104

#define IMX6QDL_CLK_AHB				105

#define IMX6QDL_CLK_APBH_DMA			106

#define IMX6QDL_CLK_ASRC			107

#define IMX6QDL_CLK_CAN1_IPG			108

#define IMX6QDL_CLK_CAN1_SERIAL			109

#define IMX6QDL_CLK_CAN2_IPG			110

#define IMX6QDL_CLK_CAN2_SERIAL			111

#define IMX6QDL_CLK_ECSPI1			112

#define IMX6QDL_CLK_ECSPI2			113

#define IMX6QDL_CLK_ECSPI3			114

#define IMX6QDL_CLK_ECSPI4			115

#define IMX6Q_CLK_ECSPI5			116

#define IMX6DL_CLK_I2C4				116

#define IMX6QDL_CLK_ENET			117

#define IMX6QDL_CLK_ESAI			118

#define IMX6QDL_CLK_GPT_IPG			119

#define IMX6QDL_CLK_GPT_IPG_PER			120

#define IMX6QDL_CLK_GPU2D_CORE			121

#define IMX6QDL_CLK_GPU3D_CORE			122

#define IMX6QDL_CLK_HDMI_IAHB			123

#define IMX6QDL_CLK_HDMI_ISFR			124

#define IMX6QDL_CLK_I2C1			125

#define IMX6QDL_CLK_I2C2			126

#define IMX6QDL_CLK_I2C3			127

#define IMX6QDL_CLK_IIM				128

#define IMX6QDL_CLK_ENFC			129

#define IMX6QDL_CLK_IPU1			130

#define IMX6QDL_CLK_IPU1_DI0			131

#define IMX6QDL_CLK_IPU1_DI1			132

#define IMX6QDL_CLK_IPU2			133

#define IMX6QDL_CLK_IPU2_DI0			134

#define IMX6QDL_CLK_LDB_DI0			135

#define IMX6QDL_CLK_LDB_DI1			136

#define IMX6QDL_CLK_IPU2_DI1			137

#define IMX6QDL_CLK_HSI_TX			138

#define IMX6QDL_CLK_MLB				139

#define IMX6QDL_CLK_MMDC_CH0_AXI		140

#define IMX6QDL_CLK_MMDC_CH1_AXI		141

#define IMX6QDL_CLK_OCRAM			142

#define IMX6QDL_CLK_OPENVG_AXI			143

#define IMX6QDL_CLK_PCIE_AXI			144

#define IMX6QDL_CLK_PWM1			145

#define IMX6QDL_CLK_PWM2			146

#define IMX6QDL_CLK_PWM3			147

#define IMX6QDL_CLK_PWM4			148

#define IMX6QDL_CLK_PER1_BCH			149

#define IMX6QDL_CLK_GPMI_BCH_APB		150

#define IMX6QDL_CLK_GPMI_BCH			151

#define IMX6QDL_CLK_GPMI_IO			152

#define IMX6QDL_CLK_GPMI_APB			153

#define IMX6QDL_CLK_SATA			154

#define IMX6QDL_CLK_SDMA			155

#define IMX6QDL_CLK_SPBA			156

#define IMX6QDL_CLK_SSI1			157

#define IMX6QDL_CLK_SSI2			158

#define IMX6QDL_CLK_SSI3			159

#define IMX6QDL_CLK_UART_IPG			160

#define IMX6QDL_CLK_UART_SERIAL			161

#define IMX6QDL_CLK_USBOH3			162

#define IMX6QDL_CLK_USDHC1			163

#define IMX6QDL_CLK_USDHC2			164

#define IMX6QDL_CLK_USDHC3			165

#define IMX6QDL_CLK_USDHC4			166

#define IMX6QDL_CLK_VDO_AXI			167

#define IMX6QDL_CLK_VPU_AXI			168

#define IMX6QDL_CLK_CKO1			169

#define IMX6QDL_CLK_PLL1_SYS			170

#define IMX6QDL_CLK_PLL2_BUS			171

#define IMX6QDL_CLK_PLL3_USB_OTG		172

#define IMX6QDL_CLK_PLL4_AUDIO			173

#define IMX6QDL_CLK_PLL5_VIDEO			174

#define IMX6QDL_CLK_PLL8_MLB			175

#define IMX6QDL_CLK_PLL7_USB_HOST		176

#define IMX6QDL_CLK_PLL6_ENET			177

#define IMX6QDL_CLK_SSI1_IPG			178

#define IMX6QDL_CLK_SSI2_IPG			179

#define IMX6QDL_CLK_SSI3_IPG			180

#define IMX6QDL_CLK_ROM				181

#define IMX6QDL_CLK_USBPHY1			182

#define IMX6QDL_CLK_USBPHY2			183

#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184

#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185

#define IMX6QDL_CLK_SATA_REF			186

#define IMX6QDL_CLK_SATA_REF_100M		187

#define IMX6QDL_CLK_PCIE_REF			188

#define IMX6QDL_CLK_PCIE_REF_125M		189

#define IMX6QDL_CLK_ENET_REF			190

#define IMX6QDL_CLK_USBPHY1_GATE		191

#define IMX6QDL_CLK_USBPHY2_GATE		192

#define IMX6QDL_CLK_PLL4_POST_DIV		193

#define IMX6QDL_CLK_PLL5_POST_DIV		194

#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195

#define IMX6QDL_CLK_EIM_SLOW			196

#define IMX6QDL_CLK_SPDIF			197

#define IMX6QDL_CLK_CKO2_SEL			198

#define IMX6QDL_CLK_CKO2_PODF			199

#define IMX6QDL_CLK_CKO2			200

#define IMX6QDL_CLK_CKO				201

#define IMX6QDL_CLK_VDOA			202

#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203

#define IMX6QDL_CLK_LVDS1_SEL			204

#define IMX6QDL_CLK_LVDS2_SEL			205

#define IMX6QDL_CLK_LVDS1_GATE			206

#define IMX6QDL_CLK_LVDS2_GATE			207

#define IMX6QDL_CLK_ESAI_AHB			208

#define IMX6QDL_CLK_END				209



#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */