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Commit d16adaf0 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu',... 

Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next

* clk-mvebu-spdx:
  clk: mvebu: armada-37xx-periph: switch to SPDX license identifier

* clk-meson:
  clk: meson: add gen_clk
  clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
  clk: meson-axg: add clocks required by pcie driver
  clk: meson: remove unused clk-audio-divider driver
  clk: meson: stop rate propagation for audio clocks
  clk: meson: axg: add the audio clock controller driver
  clk: meson: add axg audio sclk divider driver
  clk: meson: add triple phase clock driver
  clk: meson: add clk-phase clock driver
  clk: meson: clean-up meson clock configuration
  clk: meson: remove obsolete register access
  clk: meson: expose GEN_CLK clkid
  clk: meson-axg: add pcie and mipi clock bindings
  dt-bindings: clock: add meson axg audio clock controller bindings
  clk: meson: audio-divider is one based
  clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL

* clk-imx7d-mu:
  :  - i.MX7D mailbox clk support
  clk: imx7d: add IMX7D_MU_ROOT_CLK

* clk-imx-init-array-cleanup:
  :  - i.MX clk init arrays removed in place of CLK_IS_CRITICAL
  clk: imx6sx: remove clks_init_on array
  clk: imx6sl: remove clks_init_on array
  clk: imx6q: remove clks_init_on array

* clk-rockchip:
  clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
  clk: rockchip: fix clk_i2sout parent selection bits on rk3399
  clk: rockchip: add clock controller for px30
  clk: rockchip: add support for half divider
  dt-bindings: add bindings for px30 clock controller
  clk: rockchip: add dt-binding header for px30
parents 13905463 66c7bb7c 166f3a8a 30343897 566f5b67 ee3d212d

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

0 → 100644
+56 −0
Original line number Diff line number Diff line 
* Amlogic AXG Audio Clock Controllers



The Amlogic AXG audio clock controller generates and supplies clock to the

other elements of the audio subsystem, such as fifos, i2s, spdif and pdm

devices.



Required Properties:



- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

		  in clock-names.

- clock-names	: must contain the following:

		  * "pclk" - Main peripheral bus clock

		  may contain the following:

		  * "mst_in[0-7]" - 8 input plls to generate clock signals

		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external

				      components.

		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external

				       components.

- resets	: phandle of the internal reset line

- #clock-cells	: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be

used in device tree sources.



Example:



clkc_audio: clock-controller@0 {

	compatible = "amlogic,axg-audio-clkc";

	reg = <0x0 0x0 0x0 0xb4>;

	#clock-cells = <1>;



	clocks = <&clkc CLKID_AUDIO>,

		 <&clkc CLKID_MPLL0>,

		 <&clkc CLKID_MPLL1>,

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_MPLL3>,

		 <&clkc CLKID_HIFI_PLL>,

		 <&clkc CLKID_FCLK_DIV3>,

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_GP0_PLL>;

	clock-names = "pclk",

		      "mst_in0",

		      "mst_in1",

		      "mst_in2",

		      "mst_in3",

		      "mst_in4",

		      "mst_in5",

		      "mst_in6",

		      "mst_in7";

	resets = <&reset RESET_AUDIO>;

};

Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt

0 → 100644
+65 −0
Original line number Diff line number Diff line 
* Rockchip PX30 Clock and Reset Unit



The PX30 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"

- compatible: CRU should be "rockchip,px30-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "i2sx_clkin" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional



Example: Clock controller node:



	pmucru: clock-controller@ff2bc000 {

		compatible = "rockchip,px30-pmucru";

		reg = <0x0 0xff2bc000 0x0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	cru: clock-controller@ff2b0000 {

		compatible = "rockchip,px30-cru";

		reg = <0x0 0xff2b0000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff030000 {

		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff030000 0x0 0x100>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;

		clock-names = "baudclk", "apb_pclk";

		reg-shift = <2>;

		reg-io-width = <4>;

	};

drivers/clk/imx/clk-imx6q.c

+2 −12
Original line number Diff line number Diff line
@@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; 
static struct clk *clk[IMX6QDL_CLK_END];

static struct clk_onecell_data clk_data;



static unsigned int const clks_init_on[] __initconst = {

	IMX6QDL_CLK_MMDC_CH0_AXI,

	IMX6QDL_CLK_ROM,

	IMX6QDL_CLK_ARM,

};



static struct clk_div_table clk_enet_ref_table[] = {

	{ .val = 0, .div = 20, },

	{ .val = 1, .div = 10, },
@@ -417,7 +411,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *anatop_base, *base;

	int i;

	int ret;



	clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -794,7 +787,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "mlb_podf",   base + 0x74, 18);

	else

		clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);

	clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);

	clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2_flags("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);

	clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);

	clk[IMX6QDL_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);

	clk[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
@@ -808,7 +801,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[IMX6QDL_CLK_GPMI_BCH]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);

	clk[IMX6QDL_CLK_GPMI_IO]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);

	clk[IMX6QDL_CLK_GPMI_APB]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);

	clk[IMX6QDL_CLK_ROM]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);

	clk[IMX6QDL_CLK_ROM]          = imx_clk_gate2_flags("rom",     "ahb",               base + 0x7c, 0, CLK_IS_CRITICAL);

	clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ahb",               base + 0x7c, 4);

	clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);

	clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
@@ -878,9 +871,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	 */

	clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);



	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

		clk_prepare_enable(clk[clks_init_on[i]]);



	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {

		clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);

		clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);

drivers/clk/imx/clk-imx6sl.c

+0 −12
Original line number Diff line number Diff line
@@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data; 
static void __iomem *ccm_base;

static void __iomem *anatop_base;



static const u32 clks_init_on[] __initconst = {

	IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,

};



/*

 * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken

 *           during WAIT mode entry process could cause cache memory
@@ -195,7 +191,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *base;

	int i;

	int ret;



	clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -426,13 +421,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
		pr_warn("%s: failed to set AHB clock rate %d!\n",

			__func__, ret);



	/*

	 * Make sure those always on clocks are enabled to maintain the correct

	 * usecount and enabling/disabling of parent PLLs.

	 */

	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

		clk_prepare_enable(clks[clks_init_on[i]]);



	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {

		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);

		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);

drivers/clk/imx/clk-imx6sx.c

+14 −26
Original line number Diff line number Diff line
@@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; 
static struct clk *clks[IMX6SX_CLK_CLK_END];

static struct clk_onecell_data clk_data;



static int const clks_init_on[] __initconst = {

	IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,

	IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,

	IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,

	IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,

	IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,

};



static const struct clk_div_table clk_enet_ref_table[] = {

	{ .val = 0, .div = 20, },

	{ .val = 1, .div = 10, },
@@ -142,7 +134,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
{

	struct device_node *np;

	void __iomem *base;

	int i;



	clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -332,7 +323,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_QSPI1_PODF]         = imx_clk_divider("qspi1_podf",     "qspi1_sel",         base + 0x1c, 26,   3);

	clks[IMX6SX_CLK_EIM_SLOW_PODF]      = imx_clk_divider("eim_slow_podf",  "eim_slow_sel",      base + 0x1c, 23,   3);

	clks[IMX6SX_CLK_LCDIF2_PODF]        = imx_clk_divider("lcdif2_podf",    "lcdif2_pred",       base + 0x1c, 20,   3);

	clks[IMX6SX_CLK_PERCLK]             = imx_clk_divider("perclk",         "perclk_sel",        base + 0x1c, 0,    6);

	clks[IMX6SX_CLK_PERCLK]             = imx_clk_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_VID_PODF]           = imx_clk_divider("vid_podf",       "vid_sel",           base + 0x20, 24,   2);

	clks[IMX6SX_CLK_CAN_PODF]           = imx_clk_divider("can_podf",       "can_sel",           base + 0x20, 2,    6);

	clks[IMX6SX_CLK_USDHC4_PODF]        = imx_clk_divider("usdhc4_podf",    "usdhc4_sel",        base + 0x24, 22,   3);
@@ -380,8 +371,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 


	/*                                            name             parent_name          reg         shift */

	/* CCGR0 */

	clks[IMX6SX_CLK_AIPS_TZ1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);

	clks[IMX6SX_CLK_AIPS_TZ2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);

	clks[IMX6SX_CLK_AIPS_TZ1]     = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_AIPS_TZ2]     = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);

	clks[IMX6SX_CLK_ASRC_MEM]     = imx_clk_gate2_shared("asrc_mem", "ahb",             base + 0x68, 6, &share_count_asrc);

	clks[IMX6SX_CLK_ASRC_IPG]     = imx_clk_gate2_shared("asrc_ipg", "ahb",             base + 0x68, 6, &share_count_asrc);
@@ -394,7 +385,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_podf",          base + 0x68, 20);

	clks[IMX6SX_CLK_DCIC1]        = imx_clk_gate2("dcic1",         "display_podf",      base + 0x68, 24);

	clks[IMX6SX_CLK_DCIC2]        = imx_clk_gate2("dcic2",         "display_podf",      base + 0x68, 26);

	clks[IMX6SX_CLK_AIPS_TZ3]     = imx_clk_gate2("aips_tz3",      "ahb",               base + 0x68, 30);

	clks[IMX6SX_CLK_AIPS_TZ3]     = imx_clk_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL);



	/* CCGR1 */

	clks[IMX6SX_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_podf",        base + 0x6c, 0);
@@ -407,7 +398,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_ESAI_EXTAL]   = imx_clk_gate2_shared("esai_extal", "esai_podf",     base + 0x6c, 16, &share_count_esai);

	clks[IMX6SX_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);

	clks[IMX6SX_CLK_ESAI_MEM]     = imx_clk_gate2_shared("esai_mem",   "ahb",           base + 0x6c, 16, &share_count_esai);

	clks[IMX6SX_CLK_WAKEUP]       = imx_clk_gate2("wakeup",        "ipg",               base + 0x6c, 18);

	clks[IMX6SX_CLK_WAKEUP]       = imx_clk_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_GPT_BUS]      = imx_clk_gate2("gpt_bus",       "perclk",            base + 0x6c, 20);

	clks[IMX6SX_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",    "perclk",            base + 0x6c, 22);

	clks[IMX6SX_CLK_GPU]          = imx_clk_gate2("gpu",           "gpu_core_podf",     base + 0x6c, 26);
@@ -420,10 +411,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_I2C3]         = imx_clk_gate2("i2c3",          "perclk",            base + 0x70, 10);

	clks[IMX6SX_CLK_OCOTP]        = imx_clk_gate2("ocotp",         "ipg",               base + 0x70, 12);

	clks[IMX6SX_CLK_IOMUXC]       = imx_clk_gate2("iomuxc",        "lcdif1_podf",       base + 0x70, 14);

	clks[IMX6SX_CLK_IPMUX1]       = imx_clk_gate2("ipmux1",        "ahb",               base + 0x70, 16);

	clks[IMX6SX_CLK_IPMUX2]       = imx_clk_gate2("ipmux2",        "ahb",               base + 0x70, 18);

	clks[IMX6SX_CLK_IPMUX3]       = imx_clk_gate2("ipmux3",        "ahb",               base + 0x70, 20);

	clks[IMX6SX_CLK_TZASC1]       = imx_clk_gate2("tzasc1",        "mmdc_podf",         base + 0x70, 22);

	clks[IMX6SX_CLK_IPMUX1]       = imx_clk_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_IPMUX2]       = imx_clk_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_IPMUX3]       = imx_clk_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_TZASC1]       = imx_clk_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_LCDIF_APB]    = imx_clk_gate2("lcdif_apb",     "display_podf",      base + 0x70, 28);

	clks[IMX6SX_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",       "display_podf",      base + 0x70, 30);
@@ -437,15 +428,15 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_div_sel",   base + 0x74, 12);

	clks[IMX6SX_CLK_QSPI1]        = imx_clk_gate2("qspi1",         "qspi1_podf",        base + 0x74, 14);

	clks[IMX6SX_CLK_MLB]          = imx_clk_gate2("mlb",           "ahb",               base + 0x74, 18);

	clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast",  "mmdc_podf",         base + 0x74, 20);

	clks[IMX6SX_CLK_MMDC_P0_IPG]  = imx_clk_gate2("mmdc_p0_ipg",   "ipg",               base + 0x74, 24);

	clks[IMX6SX_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ocram_podf",        base + 0x74, 28);

	clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_MMDC_P0_IPG]  = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_OCRAM]        = imx_clk_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL);



	/* CCGR4 */

	clks[IMX6SX_CLK_PCIE_AXI]     = imx_clk_gate2("pcie_axi",      "display_podf",      base + 0x78, 0);

	clks[IMX6SX_CLK_QSPI2]        = imx_clk_gate2("qspi2",         "qspi2_podf",        base + 0x78, 10);

	clks[IMX6SX_CLK_PER1_BCH]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);

	clks[IMX6SX_CLK_PER2_MAIN]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);

	clks[IMX6SX_CLK_PER2_MAIN]    = imx_clk_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_PWM1]         = imx_clk_gate2("pwm1",          "perclk",            base + 0x78, 16);

	clks[IMX6SX_CLK_PWM2]         = imx_clk_gate2("pwm2",          "perclk",            base + 0x78, 18);

	clks[IMX6SX_CLK_PWM3]         = imx_clk_gate2("pwm3",          "perclk",            base + 0x78, 20);
@@ -456,7 +447,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_GPMI_APB]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);



	/* CCGR5 */

	clks[IMX6SX_CLK_ROM]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);

	clks[IMX6SX_CLK_ROM]          = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);

	clks[IMX6SX_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);

	clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);

	clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
@@ -502,9 +493,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clk_data.clk_num = ARRAY_SIZE(clks);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

		clk_prepare_enable(clks[clks_init_on[i]]);



	if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {

		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);

		clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);