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Commit d0fc30b4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: Add dev_pm_ops for gpucc"

parents bed829fe 8e3ec5db

drivers/clk/qcom/camcc-sm6150.c

+22 −8
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ static struct pll_vco cam_cc_pll_vco[] = { 
};



/* 600MHz configuration */

static const struct alpha_pll_config cam_cc_pll0_config = {

static struct alpha_pll_config cam_cc_pll0_config = {

	.l = 0x1F,

	.alpha_u = 0x40,

	.alpha_en_mask = BIT(24),
@@ -175,6 +175,7 @@ static struct clk_alpha_pll cam_cc_pll0_out_aux = { 
	.offset = 0x0,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.config = &cam_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll0_out_aux",
@@ -191,7 +192,7 @@ static struct clk_alpha_pll cam_cc_pll0_out_aux = { 
};



/* 808MHz configuration */

static const struct alpha_pll_config cam_cc_pll1_config = {

static struct alpha_pll_config cam_cc_pll1_config = {

	.l = 0x2A,

	.alpha_u = 0x15,

	.alpha = 0x55555555,
@@ -208,6 +209,7 @@ static struct clk_alpha_pll cam_cc_pll1_out_aux = { 
	.offset = 0x1000,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.config = &cam_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll1_out_aux",
@@ -224,7 +226,7 @@ static struct clk_alpha_pll cam_cc_pll1_out_aux = { 
};



/* 960MHz configuration */

static const struct alpha_pll_config cam_cc_pll2_config = {

static struct alpha_pll_config cam_cc_pll2_config = {

	.l = 0x32,

	.vco_val = 0x0 << 20,

	.vco_mask = 0x3 << 20,
@@ -241,6 +243,7 @@ static struct clk_alpha_pll cam_cc_pll2_out_early = { 
	.offset = 0x2000,

	.vco_table = cam_cc_pll2_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll2_vco),

	.config = &cam_cc_pll2_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll2_out_early",
@@ -267,7 +270,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { 
};



/* 1080MHz configuration */

static const struct alpha_pll_config cam_cc_pll3_config = {

static struct alpha_pll_config cam_cc_pll3_config = {

	.l = 0x38,

	.alpha_u = 0x40,

	.alpha_en_mask = BIT(24),
@@ -283,6 +286,7 @@ static struct clk_alpha_pll cam_cc_pll3_out_main = { 
	.offset = 0x3000,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.config = &cam_cc_pll3_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll3_out_main",
@@ -345,6 +349,7 @@ static struct clk_rcg2 cam_cc_cci_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_5,

	.freq_tbl = ftbl_cam_cc_cci_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_cci_clk_src",

		.parent_names = cam_cc_parent_names_5,
@@ -374,6 +379,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_2,

	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_cphy_rx_clk_src",

		.parent_names = cam_cc_parent_names_2,
@@ -403,6 +409,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_csi0phytimer_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -423,6 +430,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_csi1phytimer_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -443,6 +451,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_csi2phytimer_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -471,6 +480,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_fast_ahb_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -781,6 +791,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_3,

	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_mclk0_clk_src",

		.parent_names = cam_cc_parent_names_3,
@@ -800,6 +811,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_3,

	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_mclk1_clk_src",

		.parent_names = cam_cc_parent_names_3,
@@ -819,6 +831,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_3,

	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_mclk2_clk_src",

		.parent_names = cam_cc_parent_names_3,
@@ -838,6 +851,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_3,

	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_mclk3_clk_src",

		.parent_names = cam_cc_parent_names_3,
@@ -1761,13 +1775,13 @@ static int cam_cc_sm6150_probe(struct platform_device *pdev) 
	}



	clk_alpha_pll_configure(&cam_cc_pll0_out_aux, regmap,

				&cam_cc_pll0_config);

				cam_cc_pll0_out_aux.config);

	clk_alpha_pll_configure(&cam_cc_pll1_out_aux, regmap,

				&cam_cc_pll1_config);

				cam_cc_pll1_out_aux.config);

	clk_alpha_pll_configure(&cam_cc_pll2_out_early, regmap,

				&cam_cc_pll2_config);

				cam_cc_pll2_out_early.config);

	clk_alpha_pll_configure(&cam_cc_pll3_out_main, regmap,

				&cam_cc_pll3_config);

				cam_cc_pll3_out_main.config);



	ret = qcom_cc_really_probe(pdev, &cam_cc_sm6150_desc, regmap);

	if (ret) {

drivers/clk/qcom/dispcc-sm6150.c

+4 −2
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static struct pll_vco disp_cc_pll_vco[] = { 
};



/* 576MHz configuration */

static const struct alpha_pll_config disp_cc_pll0_config = {

static struct alpha_pll_config disp_cc_pll0_config = {

	.l = 0x1E,

	.vco_val = 0x2 << 20,

	.vco_mask = 0x3 << 20,
@@ -144,6 +144,7 @@ static struct clk_alpha_pll disp_cc_pll0_out_main = { 
	.vco_table = disp_cc_pll_vco,

	.num_vco = ARRAY_SIZE(disp_cc_pll_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &disp_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll0_out_main",
@@ -269,6 +270,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
	.hid_width = 5,

	.parent_map = disp_cc_parent_map_0,

	.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_link_clk_src",

		.parent_names = disp_cc_parent_names_0,
@@ -850,7 +852,7 @@ static int disp_cc_sm6150_probe(struct platform_device *pdev) 
	}



	clk_alpha_pll_configure(&disp_cc_pll0_out_main, regmap,

				&disp_cc_pll0_config);

				disp_cc_pll0_out_main.config);



	ret = qcom_cc_really_probe(pdev, &disp_cc_sm6150_desc, regmap);

	if (ret) {

drivers/clk/qcom/gpucc-sm6150.c

+44 −18
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static struct pll_vco gpu_cc_pll_vco[] = { 
};



/* 1020MHz configuration */

static const struct alpha_pll_config gpu_pll0_config = {

static struct alpha_pll_config gpu_pll0_config = {

	.l = 0x35,

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,
@@ -116,7 +116,7 @@ static const struct alpha_pll_config gpu_pll0_config = { 
};



/* 930MHz configuration */

static const struct alpha_pll_config gpu_pll1_config = {

static struct alpha_pll_config gpu_pll1_config = {

	.l = 0x30,

	.config_ctl_val = 0x4001055b,

	.test_ctl_hi_val = 0x1,
@@ -134,6 +134,7 @@ static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { 
	.vco_table = gpu_cc_pll_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &gpu_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_pll0_out_aux2",
@@ -154,6 +155,7 @@ static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { 
	.vco_table = gpu_cc_pll_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &gpu_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_pll1_out_aux2",
@@ -513,6 +515,39 @@ static const struct of_device_id gpu_cc_sm6150_match_table[] = { 
};

MODULE_DEVICE_TABLE(of, gpu_cc_sm6150_match_table);



static void gpu_cc_sm6150_configure(struct regmap *regmap)

{

	unsigned int value, mask;



	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */

	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;

	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;

	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;

	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,

							mask, value);



	/* After POR, Clock Ramp Controller(CRC) will be in bypass mode.

	 * Software needs to do the following operation to enable the CRC

	 * for GFX3D clock and divide the input clock by div by 2.

	 */

	regmap_update_bits(regmap, GFX3D_CRC_MND_CFG, 0x00015011, 0x00015011);

	regmap_update_bits(regmap,

			GFX3D_CRC_SID_FSM_CTRL, 0x00800000, 0x00800000);

}



static int gpu_cc_sm6150_resume(struct device *dev)

{

	struct regmap *regmap = dev_get_drvdata(dev);



	gpu_cc_sm6150_configure(regmap);



	return 0;

}



static const struct dev_pm_ops gpu_cc_sm6150_pm_ops = {

	.restore_early = gpu_cc_sm6150_resume,

};



static void gpucc_sm6150_fixup_sa6155(struct platform_device *pdev)

{

	vdd_cx.num_levels = VDD_NUM_SA6155;
@@ -521,13 +556,14 @@ static void gpucc_sm6150_fixup_sa6155(struct platform_device *pdev) 
	vdd_mx.cur_level = VDD_MX_NUM_SA6155;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 0;

	gpu_cc_gx_gfx3d_clk_src.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src_sa6155;



	pdev->dev.driver->pm =  &gpu_cc_sm6150_pm_ops;

}



static int gpu_cc_sm6150_probe(struct platform_device *pdev)

{

	struct regmap *regmap;

	int ret;

	unsigned int value, mask;

	int is_sa6155;



	/* Get CX voltage regulator for CX and GMU clocks. */
@@ -560,9 +596,9 @@ static int gpu_cc_sm6150_probe(struct platform_device *pdev) 
	}



	clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap,

					&gpu_pll0_config);

					gpu_cc_pll0_out_aux2.config);

	clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap,

					&gpu_pll1_config);

					gpu_cc_pll1_out_aux2.config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6150_desc, regmap);

	if (ret) {
@@ -570,20 +606,10 @@ static int gpu_cc_sm6150_probe(struct platform_device *pdev) 
		return ret;

	}



	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */

	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;

	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;

	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;

	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,

							mask, value);

	gpu_cc_sm6150_configure(regmap);



	/* After POR, Clock Ramp Controller(CRC) will be in bypass mode.

	 * Software needs to do the following operation to enable the CRC

	 * for GFX3D clock and divide the input clock by div by 2.

	 */

	regmap_update_bits(regmap, GFX3D_CRC_MND_CFG, 0x00015011, 0x00015011);

	regmap_update_bits(regmap,

			GFX3D_CRC_SID_FSM_CTRL, 0x00800000, 0x00800000);

	if (is_sa6155)

		dev_set_drvdata(&pdev->dev, regmap);



	dev_info(&pdev->dev, "Registered GPU CC clocks\n");

drivers/clk/qcom/scc-sm6150.c

+11 −3
Original line number Diff line number Diff line
@@ -37,8 +37,8 @@ 
static DEFINE_VDD_REGULATORS(vdd_scc_cx, VDD_NUM, 1, vdd_corner);



enum {

	P_AON_SLEEP_CLK,

	P_AOSS_CC_RO_CLK,

	P_AON_SLEEP_CLK,

	P_CORE_PI_CXO_CLK,

	P_QDSP6SS_PLL_OUT_AUX,

	P_SCC_PLL_OUT_AUX,
@@ -74,7 +74,7 @@ static struct pll_vco scc_pll_vco[] = { 
};



/* 600MHz configuration */

static const struct alpha_pll_config scc_pll_config = {

static struct alpha_pll_config scc_pll_config = {

	.l = 0x1F,

	.alpha_u = 0x40,

	.alpha_en_mask = BIT(24),
@@ -93,6 +93,7 @@ static struct clk_alpha_pll scc_pll_out_aux2 = { 
	.offset = 0x0,

	.vco_table = scc_pll_vco,

	.num_vco = ARRAY_SIZE(scc_pll_vco),

	.config = &scc_pll_config,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_pll_out_aux2",

		.parent_names = (const char *[]){ "bi_tcxo" },
@@ -141,6 +142,7 @@ static struct clk_rcg2 scc_main_rcg_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_main_rcg_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_main_rcg_clk_src",

		.parent_names = scc_parent_names_0,
@@ -200,6 +202,7 @@ static struct clk_rcg2 scc_qupv3_se1_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_qupv3_se0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_qupv3_se1_clk_src",

		.parent_names = scc_parent_names_0,
@@ -221,6 +224,7 @@ static struct clk_rcg2 scc_qupv3_se2_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_qupv3_se0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_qupv3_se2_clk_src",

		.parent_names = scc_parent_names_0,
@@ -242,6 +246,7 @@ static struct clk_rcg2 scc_qupv3_se3_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_qupv3_se0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_qupv3_se3_clk_src",

		.parent_names = scc_parent_names_0,
@@ -263,6 +268,7 @@ static struct clk_rcg2 scc_qupv3_se4_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_qupv3_se0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_qupv3_se4_clk_src",

		.parent_names = scc_parent_names_0,
@@ -284,6 +290,7 @@ static struct clk_rcg2 scc_qupv3_se5_clk_src = { 
	.hid_width = 5,

	.parent_map = scc_parent_map_0,

	.freq_tbl = ftbl_scc_qupv3_se0_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "scc_qupv3_se5_clk_src",

		.parent_names = scc_parent_names_0,
@@ -571,7 +578,8 @@ static int scc_sm6150_probe(struct platform_device *pdev) 
		return PTR_ERR(regmap);

	}



	clk_alpha_pll_configure(&scc_pll_out_aux2, regmap, &scc_pll_config);

	clk_alpha_pll_configure(&scc_pll_out_aux2, regmap,

			scc_pll_out_aux2.config);



	ret = qcom_cc_really_probe(pdev, &scc_sm6150_desc, regmap);

	if (ret) {

drivers/clk/qcom/videocc-sm6150.c

+3 −2
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static struct pll_vco video_cc_pll_vco[] = { 
};



/* 600MHz configuration */

static const struct alpha_pll_config video_pll0_config = {

static struct alpha_pll_config video_pll0_config = {

	.l = 0x1F,

	.alpha_u = 0x40,

	.alpha = 0x00,
@@ -103,6 +103,7 @@ static struct clk_alpha_pll video_pll0_out_main = { 
	.vco_table = video_cc_pll_vco,

	.num_vco = ARRAY_SIZE(video_cc_pll_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &video_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "video_pll0_out_main",
@@ -364,7 +365,7 @@ static int video_cc_sm6150_probe(struct platform_device *pdev) 
	}



	clk_alpha_pll_configure(&video_pll0_out_main, regmap,

						&video_pll0_config);

					video_pll0_out_main.config);



	ret = qcom_cc_really_probe(pdev, &video_cc_sm6150_desc, regmap);

	if (ret) {