Commit d050a9e5 authored May 20, 2020 by Tony Truong Committed by Gerrit - the friendly Code Review server May 26, 2020

ARM: dts: msm: add LTR entry for PCIe0 on sdxprairie



add latency tolerance reporting (LTR) for PCIe0 on sdxprairie.

Change-Id: I52d2767c04412884982c4106fcb18dd34b12c4b7
Signed-off-by: Tony Truong <truong@codeaurora.org>

parent e97c6600

arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -187,6 +187,9 @@

		qcom,no-l0s-supported;

		qcom,l1-2-th-scale = <2>; /* 1us */
		qcom,l1-2-th-value = <70>;

		qcom,ep-latency = <10>;

		qcom,slv-addr-space-size = <0x40000000>;