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Commit d0128b7d authored by Gabriel FERNANDEZ's avatar Gabriel FERNANDEZ Committed by Maxime Coquelin
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ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU 



Patch adds DT entries for clockgen A9/DDR/GPU

Signed-off-by: default avatarPankaj Dev <pankaj.dev@st.com>
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
parent 7f8472c8

arch/arm/boot/dts/stih416-clock.dtsi

+70 −9
Original line number Diff line number Diff line
@@ -24,15 +24,6 @@ 
			clock-frequency = <30000000>;

		};



		/*

		 * ARM Peripheral clock for timers

		 */

		arm_periph_clk: arm_periph_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <600000000>;

		};



		/*

		 * ClockGenAs on SASG2

		 */
@@ -503,6 +494,45 @@ 
			};

		};



		/*

		 * A9 PLL

		 */

		clockgen-a9@fdde08b0 {

			reg = <0xfdde08b0 0x70>;



			clockgen_a9_pll: clockgen-a9-pll {

				#clock-cells = <1>;

				compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;

				clock-output-names = "clockgen-a9-pll-odf";

			};

		};



		/*

		 * ARM CPU related clocks

		 */

		clk_m_a9: clk-m-a9@fdde08ac {

			#clock-cells = <0>;

			compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";

			reg = <0xfdde08ac 0x4>;

			clocks = <&clockgen_a9_pll 0>,

				 <&clockgen_a9_pll 0>,

				 <&clk_m_a0_div1 2>,

				 <&clk_m_a9_ext2f_div2>;

		};



		/*

		 * ARM Peripheral clock for timers

		 */

		arm_periph_clk: clk-m-a9-periphs {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&clk_m_a9>;

			clock-div = <2>;

			clock-mult = <1>;

		};



		/*

		 * Frequency synthesizers on the SASG2

		 */
@@ -691,5 +721,36 @@ 
					      "clk-m-pix-hdmirx-0",

					      "clk-m-pix-hdmirx-1";

		};



		/*

		 * DDR PLL

		 */

		clockgen-ddr@0xfdde07d8 {

			reg = <0xfdde07d8 0x110>;



			clockgen_ddr_pll: clockgen-ddr-pll {

				#clock-cells = <1>;

				compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";



				clocks = <&clk_sysin>;

				clock-output-names = "clockgen-ddr0",

						     "clockgen-ddr1";

			};

		};



		/*

		 * GPU PLL

		 */

		clockgen-gpu@fd68ff00 {

			reg = <0xfd68ff00 0x910>;



			clockgen_gpu_pll: clockgen-gpu-pll {

				#clock-cells = <1>;

				compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";



				clocks = <&clk_sysin>;

				clock-output-names = "clockgen-gpu-pll";

			};

		};

	};

};