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Commit cfe4e37f authored by Daniel Jurgens's avatar Daniel Jurgens Committed by Jason Gunthorpe
Browse files

{net, IB}/mlx5: Change set_roce_gid to take a port number 



When in dual port mode setting a RoCE GID for any port flows through the
master ports mlx5_core_dev. Provide an interface to set the port when
sending this command.

Signed-off-by: default avatarDaniel Jurgens <danielj@mellanox.com>
Reviewed-by: default avatarParav Pandit <parav@mellanox.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent aac4492e

drivers/infiniband/hw/mlx5/main.c

+1 −1
Original line number Diff line number Diff line
@@ -475,7 +475,7 @@ static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 


	return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,

				      roce_l3_type, gid->raw, mac, vlan,

				      vlan_id);

				      vlan_id, port_num);

}



static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,

drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c

+4 −3
Original line number Diff line number Diff line
@@ -888,7 +888,8 @@ struct mlx5_fpga_conn *mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev, 
	err = mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index,

				     MLX5_ROCE_VERSION_2,

				     MLX5_ROCE_L3_TYPE_IPV6,

				     remote_ip, remote_mac, true, 0);

				     remote_ip, remote_mac, true, 0,

				     MLX5_FPGA_PORT_NUM);

	if (err) {

		mlx5_fpga_err(fdev, "Failed to set SGID: %d\n", err);

		ret = ERR_PTR(err);
@@ -954,7 +955,7 @@ struct mlx5_fpga_conn *mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev, 
	mlx5_fpga_conn_destroy_cq(conn);

err_gid:

	mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index, 0, 0, NULL,

			       NULL, false, 0);

			       NULL, false, 0, MLX5_FPGA_PORT_NUM);

err_rsvd_gid:

	mlx5_core_reserved_gid_free(fdev->mdev, conn->qp.sgid_index);

err:
@@ -982,7 +983,7 @@ void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn) 
	mlx5_fpga_conn_destroy_cq(conn);



	mlx5_core_roce_gid_set(conn->fdev->mdev, conn->qp.sgid_index, 0, 0,

			       NULL, NULL, false, 0);

			       NULL, NULL, false, 0, MLX5_FPGA_PORT_NUM);

	mlx5_core_reserved_gid_free(conn->fdev->mdev, conn->qp.sgid_index);

	kfree(conn);

}

drivers/net/ethernet/mellanox/mlx5/core/lib/gid.c

+4 −1
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ EXPORT_SYMBOL_GPL(mlx5_core_reserved_gids_count); 


int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,

			   u8 roce_version, u8 roce_l3_type, const u8 *gid,

			   const u8 *mac, bool vlan, u16 vlan_id)

			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num)

{

#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)

	u32  in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
@@ -148,6 +148,9 @@ int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 
		memcpy(addr_l3_addr, gid, gidsz);

	}



	if (MLX5_CAP_GEN(dev, num_vhca_ports) > 0)

		MLX5_SET(set_roce_address_in, in, vhca_port_num, port_num);



	MLX5_SET(set_roce_address_in, in, roce_address_index, index);

	MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);

	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));

include/linux/mlx5/driver.h

+1 −1
Original line number Diff line number Diff line
@@ -1112,7 +1112,7 @@ void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 
unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);

int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,

			   u8 roce_version, u8 roce_l3_type, const u8 *gid,

			   const u8 *mac, bool vlan, u16 vlan_id);

			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);



static inline int fw_initializing(struct mlx5_core_dev *dev)

{