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Commit cf87a88f authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'sunxi-clocks-for-4.5' of... 

Merge tag 'sunxi-clocks-for-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clocks changes for 4.5

Clock patches for the Allwinner SoCs:
  - H3 clocks
  - A10/A20 Video Engine clocks
  - DRAM gates
  - A80 special CPU clock
parents a915e30d fee3103a

Documentation/devicetree/bindings/clock/sunxi.txt

+10 −0
Original line number Diff line number Diff line
@@ -27,7 +27,9 @@ Required properties: 
	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s

	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20

	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31

	"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80

	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31

	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3

	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31

	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23

	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,6 +57,9 @@ Required properties: 
	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80

	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31

	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23

	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3

	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80

	"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10

	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13

	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock

	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
@@ -68,8 +73,10 @@ Required properties: 
	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13

	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31

	"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23

	"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3

	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80

	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80

	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock



Required properties for all clocks:

- reg : shall be the control register address for the clock.
@@ -89,6 +96,9 @@ Required properties for all clocks: 
And "allwinner,*-usb-clk" clocks also require:

- reset-cells : shall be set to 1



The "allwinner,sun4i-a10-ve-clk" clock also requires:

- reset-cells : shall be set to 0



The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:

- #reset-cells : shall be set to 1

- resets : shall be the reset control phandle for the mmc block.

drivers/clk/sunxi/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -7,14 +7,19 @@ obj-y += clk-a10-codec.o 
obj-y += clk-a10-hosc.o

obj-y += clk-a10-mod1.o

obj-y += clk-a10-pll2.o

obj-y += clk-a10-ve.o

obj-y += clk-a20-gmac.o

obj-y += clk-mod0.o

obj-y += clk-simple-gates.o

obj-y += clk-sun8i-bus-gates.o

obj-y += clk-sun8i-mbus.o

obj-y += clk-sun9i-core.o

obj-y += clk-sun9i-mmc.o

obj-y += clk-usb.o



obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o

obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o



obj-$(CONFIG_MFD_SUN6I_PRCM) += \

	clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \

	clk-sun8i-apb0.o

drivers/clk/sunxi/clk-a10-ve.c

0 → 100644
+171 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2015 Chen-Yu Tsai

 *

 * Chen-Yu Tsai <wens@csie.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/reset-controller.h>

#include <linux/slab.h>

#include <linux/spinlock.h>



static DEFINE_SPINLOCK(ve_lock);



#define SUN4I_VE_ENABLE		31

#define SUN4I_VE_DIVIDER_SHIFT	16

#define SUN4I_VE_DIVIDER_WIDTH	3

#define SUN4I_VE_RESET		0



/**

 * sunxi_ve_reset... - reset bit in ve clk registers handling

 */



struct ve_reset_data {

	void __iomem			*reg;

	spinlock_t			*lock;

	struct reset_controller_dev	rcdev;

};



static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,

				 unsigned long id)

{

	struct ve_reset_data *data = container_of(rcdev,

						  struct ve_reset_data,

						  rcdev);

	unsigned long flags;

	u32 reg;



	spin_lock_irqsave(data->lock, flags);



	reg = readl(data->reg);

	writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);



	spin_unlock_irqrestore(data->lock, flags);



	return 0;

}



static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,

				   unsigned long id)

{

	struct ve_reset_data *data = container_of(rcdev,

						  struct ve_reset_data,

						  rcdev);

	unsigned long flags;

	u32 reg;



	spin_lock_irqsave(data->lock, flags);



	reg = readl(data->reg);

	writel(reg | BIT(SUN4I_VE_RESET), data->reg);



	spin_unlock_irqrestore(data->lock, flags);



	return 0;

}



static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,

			     const struct of_phandle_args *reset_spec)

{

	if (WARN_ON(reset_spec->args_count != 0))

		return -EINVAL;



	return 0;

}



static struct reset_control_ops sunxi_ve_reset_ops = {

	.assert		= sunxi_ve_reset_assert,

	.deassert	= sunxi_ve_reset_deassert,

};



static void __init sun4i_ve_clk_setup(struct device_node *node)

{

	struct clk *clk;

	struct clk_divider *div;

	struct clk_gate *gate;

	struct ve_reset_data *reset_data;

	const char *parent;

	const char *clk_name = node->name;

	void __iomem *reg;

	int err;



	reg = of_io_request_and_map(node, 0, of_node_full_name(node));

	if (IS_ERR(reg))

		return;



	div = kzalloc(sizeof(*div), GFP_KERNEL);

	if (!div)

		goto err_unmap;



	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate)

		goto err_free_div;



	of_property_read_string(node, "clock-output-names", &clk_name);

	parent = of_clk_get_parent_name(node, 0);



	gate->reg = reg;

	gate->bit_idx = SUN4I_VE_ENABLE;

	gate->lock = &ve_lock;



	div->reg = reg;

	div->shift = SUN4I_VE_DIVIDER_SHIFT;

	div->width = SUN4I_VE_DIVIDER_WIDTH;

	div->lock = &ve_lock;



	clk = clk_register_composite(NULL, clk_name, &parent, 1,

				     NULL, NULL,

				     &div->hw, &clk_divider_ops,

				     &gate->hw, &clk_gate_ops,

				     CLK_SET_RATE_PARENT);

	if (IS_ERR(clk))

		goto err_free_gate;



	err = of_clk_add_provider(node, of_clk_src_simple_get, clk);

	if (err)

		goto err_unregister_clk;



	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);

	if (!reset_data)

		goto err_del_provider;



	reset_data->reg = reg;

	reset_data->lock = &ve_lock;

	reset_data->rcdev.nr_resets = 1;

	reset_data->rcdev.ops = &sunxi_ve_reset_ops;

	reset_data->rcdev.of_node = node;

	reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;

	reset_data->rcdev.of_reset_n_cells = 0;

	err = reset_controller_register(&reset_data->rcdev);

	if (err)

		goto err_free_reset;



	return;



err_free_reset:

	kfree(reset_data);

err_del_provider:

	of_clk_del_provider(node);

err_unregister_clk:

	clk_unregister(clk);

err_free_gate:

	kfree(gate);

err_free_div:

	kfree(div);

err_unmap:

	iounmap(reg);

}

CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",

	       sun4i_ve_clk_setup);

drivers/clk/sunxi/clk-simple-gates.c

+14 −0
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk", 
	       sunxi_simple_gates_init);

CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",

	       sunxi_simple_gates_init);

CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-gates-clk",

	       sunxi_simple_gates_init);



static const int sun4i_a10_ahb_critical_clocks[] __initconst = {

	14,	/* ahb_sdram */
@@ -158,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk", 
	       sun4i_a10_ahb_init);

CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",

	       sun4i_a10_ahb_init);



static const int sun4i_a10_dram_critical_clocks[] __initconst = {

	15,	/* dram_output */

};



static void __init sun4i_a10_dram_init(struct device_node *node)

{

	sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,

				 ARRAY_SIZE(sun4i_a10_dram_critical_clocks));

}

CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",

	       sun4i_a10_dram_init);

drivers/clk/sunxi/clk-sun8i-apb0.c

+68 −12
Original line number Diff line number Diff line
@@ -17,13 +17,77 @@ 
#include <linux/clk-provider.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>



static struct clk *sun8i_a23_apb0_register(struct device_node *node,

					   void __iomem *reg)

{

	const char *clk_name = node->name;

	const char *clk_parent;

	struct clk *clk;

	int ret;



	clk_parent = of_clk_get_parent_name(node, 0);

	if (!clk_parent)

		return ERR_PTR(-EINVAL);



	of_property_read_string(node, "clock-output-names", &clk_name);



	/* The A23 APB0 clock is a standard 2 bit wide divider clock */

	clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,

				   0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	if (IS_ERR(clk))

		return clk;



	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);

	if (ret)

		goto err_unregister;



	return clk;



err_unregister:

	clk_unregister_divider(clk);



	return ERR_PTR(ret);

}



static void sun8i_a23_apb0_setup(struct device_node *node)

{

	void __iomem *reg;

	struct resource res;

	struct clk *clk;



	reg = of_io_request_and_map(node, 0, of_node_full_name(node));

	if (IS_ERR(reg)) {

		/*

		 * This happens with clk nodes instantiated through mfd,

		 * as those do not have their resources assigned in the

		 * device tree. Do not print an error in this case.

		 */

		if (PTR_ERR(reg) != -EINVAL)

			pr_err("Could not get registers for a23-apb0-clk\n");



		return;

	}



	clk = sun8i_a23_apb0_register(node, reg);

	if (IS_ERR(clk))

		goto err_unmap;



	return;



err_unmap:

	iounmap(reg);

	of_address_to_resource(node, 0, &res);

	release_mem_region(res.start, resource_size(&res));

}

CLK_OF_DECLARE(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",

	       sun8i_a23_apb0_setup);



static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;

	const char *clk_name = np->name;

	const char *clk_parent;

	struct resource *r;

	void __iomem *reg;

	struct clk *clk;
@@ -33,19 +97,11 @@ static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev) 
	if (IS_ERR(reg))

		return PTR_ERR(reg);



	clk_parent = of_clk_get_parent_name(np, 0);

	if (!clk_parent)

		return -EINVAL;



	of_property_read_string(np, "clock-output-names", &clk_name);



	/* The A23 APB0 clock is a standard 2 bit wide divider clock */

	clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,

				   0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);

	clk = sun8i_a23_apb0_register(np, reg);

	if (IS_ERR(clk))

		return PTR_ERR(clk);



	return of_clk_add_provider(np, of_clk_src_simple_get, clk);

	return 0;

}



static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {