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Commit cecf48e2 authored by Paul Mundt's avatar Paul Mundt
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sh: pci: Use I/O accessors consistently in SH7786 PCIe init code. 



Some of the existing code is flipping between __raw_xxx() and
pci_{read,write}_reg(). As the latter are just wrappers for the former,
flip over to using them consistently.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent bd792aea

arch/sh/drivers/pci/pcie-sh7786.c

+18 −17
Original line number Diff line number Diff line
@@ -304,24 +304,24 @@ static int pcie_init(struct sh7786_pcie_port *port) 
	 * LAR1/LAMR1.

	 */

	if (memsize > SZ_512M) {

		__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);

		__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,

			     chan->reg_base + SH4A_PCIELAMR1);

		pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);

		pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,

			      SH4A_PCIELAMR1);

		memsize = SZ_512M;

	} else {

		/*

		 * Otherwise just zero it out and disable it.

		 */

		__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);

		__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);

		pci_write_reg(chan, 0, SH4A_PCIELAR1);

		pci_write_reg(chan, 0, SH4A_PCIELAMR1);

	}



	/*

	 * LAR0/LAMR0 covers up to the first 512MB, which is enough to

	 * cover all of lowmem on most platforms.

	 */

	__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);

	__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);

	pci_write_reg(chan, memphys, SH4A_PCIELAR0);

	pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);



	/* Finish initialization */

	data = pci_read_reg(chan, SH4A_PCIETCTLR);
@@ -370,7 +370,7 @@ static int pcie_init(struct sh7786_pcie_port *port) 
	for (i = win = 0; i < chan->nr_resources; i++) {

		struct resource *res = chan->resources + i;

		resource_size_t size;

		u32 enable_mask;

		u32 mask;



		/*

		 * We can't use the 32-bit mode windows in legacy 29-bit
@@ -381,23 +381,24 @@ static int pcie_init(struct sh7786_pcie_port *port) 


		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));



		size = resource_size(res);



		/*

		 * The PAMR mask is calculated in units of 256kB, which

		 * keeps things pretty simple.

		 */

		__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,

			     chan->reg_base + SH4A_PCIEPAMR(win));

		size = resource_size(res);

		mask = (roundup_pow_of_two(size) / SZ_256K) - 1;

		pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));



		pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));

		pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));

		pci_write_reg(chan, RES_TO_U32_HIGH(res->start),

			      SH4A_PCIEPARH(win));

		pci_write_reg(chan, RES_TO_U32_LOW(res->start),

			      SH4A_PCIEPARL(win));



		enable_mask = MASK_PARE;

		mask = MASK_PARE;

		if (res->flags & IORESOURCE_IO)

			enable_mask |= MASK_SPC;

			mask |= MASK_SPC;



		pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));

		pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));



		win++;

	}

arch/sh/drivers/pci/pcie-sh7786.h

+7 −0
Original line number Diff line number Diff line
@@ -568,6 +568,13 @@ 


#define PCI_REG(x)		((x) + 0x40000)



#define U64_TO_U32_LOW(val)	((u32)((val) & 0x00000000ffffffffULL))

#define U64_TO_U32_HIGH(val)	((u32)((val) >> 32))

#define RES_TO_U32_LOW(val)     \

	((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))

#define RES_TO_U32_HIGH(val)    \

	((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))



static inline void

pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)

{