Merge "clk: qcom: Update DSI clk names for SDM660" (ce6cc54c) · Commits · e / devices / android_kernel_xiaomi_nabu

Documentation/devicetree/bindings/fb/mdss-pll.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@ Required properties:
		"qcom,mdss_dp_pll_14nm", "qcom,mdss_hdmi_pll_28lpm",
		"qcom,mdss_dsi_pll_7nm_v2"
		"qcom,mdss_dp_pll_sdm660",
		"qcom,mdss_dsi_pll_sdm660"
		- cell-index: Specifies the controller used
		- reg: offset and length of the register set for the device.
		- reg-names : names to refer to register sets related to this device

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+14 −7

Original line number	Diff line number	Diff line
		/* Copyright (c) 2015-2016,2018-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2015-2016,2018-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -54,6 +54,13 @@ static struct regmap_bus dsi_mux_regmap_bus = {
		.reg_read = dsi_mux_get_parent_14nm,
		};

		static const char * const dsi_vco_clk_parent_names[] = {
		#ifdef CONFIG_FB_MSM_MDSS
		"xo_board"
		#else
		"bi_tcxo"
		#endif
		};
		/* Op structures */
		static const struct clk_ops clk_ops_dsi_vco = {
		.recalc_rate = pll_vco_recalc_rate_14nm,
		@@ -78,7 +85,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_vco_clk_14nm",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.parent_names = dsi_vco_clk_parent_names,
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_ops_dsi_vco,
		@@ -91,7 +98,7 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
		.max_rate = 2600000000u,
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_shadow_vco_clk_14nm",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.parent_names = dsi_vco_clk_parent_names,
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_ops_shadow_dsi_vco,
		@@ -106,7 +113,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_vco_clk_14nm",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.parent_names = dsi_vco_clk_parent_names,
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_ops_dsi_vco,
		@@ -121,7 +128,7 @@ static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_shadow_vco_clk_14nm",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.parent_names = dsi_vco_clk_parent_names,
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_ops_shadow_dsi_vco,
		@@ -342,7 +349,7 @@ static struct clk_regmap_mux dsi1pll_pixel_clk_mux = {

		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_pixel_clk_mux",
		.name = "dsi1_phy_pll_out_dsiclk",
		.parent_names =
		(const char *[]){ "dsi1pll_pixel_clk_src",
		"dsi1pll_shadow_pixel_clk_src"},
		@@ -434,7 +441,7 @@ static struct clk_regmap_mux dsi1pll_byte_clk_mux = {

		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_byte_clk_mux",
		.name = "dsi1_phy_pll_out_byteclk",
		.parent_names =
		(const char *[]){"dsi1pll_byte_clk_src",
		"dsi1pll_shadow_byte_clk_src"},

drivers/clk/qcom/mdss/mdss-pll.c

+7 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -144,6 +144,11 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
		pll_res->pll_interface_type = MDSS_DP_PLL_14NM;
		else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_28lpm"))
		pll_res->pll_interface_type = MDSS_HDMI_PLL_28LPM;
		else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) {
		pll_res->pll_interface_type = MDSS_DSI_PLL_14NM;
		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
		pll_res->revision = 2;
		}
		else
		goto err;

		@@ -428,6 +433,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
		{.compatible = "qcom,mdss_dsi_pll_14nm"},
		{.compatible = "qcom,mdss_dp_pll_14nm"},
		{.compatible = "qcom,mdss_hdmi_pll_28lpm"},
		{.compatible = "qcom,mdss_dsi_pll_sdm660"},
		{}
		};

drivers/clk/qcom/mdss/mdss-pll.h

+10 −2

Original line number	Diff line number	Diff line
		/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -57,6 +57,7 @@ enum {

		enum {
		MDSS_PLL_TARGET_8996,
		MDSS_PLL_TARGET_SDM660,
		};

		#define DFPS_MAX_NUM_OF_FRAME_RATES 16
		@@ -212,11 +213,18 @@ struct mdss_pll_vco_calc {

		static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res)
		{
		bool ret = false;
		if (!pll_res->gdsc_base) {
		WARN(1, "gdsc_base register is not defined\n");
		return true;
		}
		return readl_relaxed(pll_res->gdsc_base) & BIT(31) ? false : true;
		if (pll_res->target_id == MDSS_PLL_TARGET_SDM660)
		ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&
		(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true;
		else
		ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ?
		false : true;
		return ret;
		}

		static inline int mdss_pll_div_prepare(struct clk_hw *hw)

drivers/clk/qcom/mmcc-sdm660.c

+5 −5

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
		* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -113,8 +113,8 @@ static const struct parent_map mmcc_parent_map_1[] = {

		static const char * const mmcc_parent_names_1[] = {
		"xo",
		"dsi0pll_byte_clk_mux",
		"dsi1pll_byte_clk_mux",
		"dsi0_phy_pll_out_byteclk",
		"dsi1_phy_pll_out_byteclk",
		"core_bi_pll_test_se",
		};

		@@ -241,8 +241,8 @@ static const struct parent_map mmcc_parent_map_8[] = {

		static const char * const mmcc_parent_names_8[] = {
		"xo",
		"dsi0pll_pixel_clk_mux",
		"dsi1pll_pixel_clk_mux",
		"dsi0_phy_pll_out_dsiclk",
		"dsi1_phy_pll_out_dsiclk",
		"core_bi_pll_test_se",
		};