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Commit ce37a0a0 authored by Pankaj Gupta's avatar Pankaj Gupta
Browse files

msm: kgsl: Always boot GMU with default CM3 config 



Ensure that CM3 configuration is always set to default value
before taking CM3 out of reset. Also make sure that we
read/modify this register when we send NMI to GMU.

Change-Id: Ic9c4506c04c5e7dd1cabf12901fa53636e2ed9c7
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
Signed-off-by: default avatarPankaj Gupta <gpankaj@codeaurora.org>
parent 260264b0

drivers/gpu/msm/adreno_a6xx_gmu.c

+10 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -351,6 +351,8 @@ static int a6xx_gmu_start(struct kgsl_device *device) 


	/* Bring GMU out of reset */

	gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0);

	/* Make sure the request completes before continuing */

	wmb();

	if (timed_poll_check(device,

			A6XX_GMU_CM3_FW_INIT_RESULT,

			0xBABEFACE,
@@ -1042,6 +1044,13 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, 
	gmu_core_regwrite(device, A6XX_GMU_AHB_FENCE_RANGE_0,

			GMU_FENCE_RANGE_MASK);



	/*

	 * Make sure that CM3 state is at reset value. Snapshot is changing

	 * NMI bit and if we boot up GMU with NMI bit set.GMU will boot straight

	 * in to NMI handler without executing __main code

	 */

	gmu_core_regwrite(device, A6XX_GMU_CM3_CFG, 0x4052);



	/* Pass chipid to GMU FW, must happen before starting GMU */



	/* Keep Core and Major bitfields unchanged */

drivers/gpu/msm/kgsl_gmu.c

+6 −3
Original line number Diff line number Diff line
@@ -964,6 +964,8 @@ static int gmu_rpmh_init(struct kgsl_device *device, 


static void send_nmi_to_gmu(struct adreno_device *adreno_dev)

{

	u32 val;



	/* Mask so there's no interrupt caused by NMI */

	adreno_write_gmureg(adreno_dev,

			ADRENO_REG_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
@@ -972,9 +974,10 @@ static void send_nmi_to_gmu(struct adreno_device *adreno_dev) 
	wmb();

	adreno_write_gmureg(adreno_dev,

		ADRENO_REG_GMU_NMI_CONTROL_STATUS, 0);

	adreno_write_gmureg(adreno_dev,

		ADRENO_REG_GMU_CM3_CFG,

		(1 << GMU_CM3_CFG_NONMASKINTR_SHIFT));



	adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, &val);

	val |= 1 << GMU_CM3_CFG_NONMASKINTR_SHIFT;

	adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, val);



	/* Make sure the NMI is invoked before we proceed*/

	wmb();