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Commit ce370bfd authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Greg Kroah-Hartman
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usb: xhci-mtk: check clock stability of U3_MAC 



This is useful to find out the root cause when the Super Speed doesn't
work. Such as when the T-PHY is switched to PCIe or SATA, and affects
Super Speed function, the check will fail.

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8465d3e4

drivers/usb/host/xhci-mtk.c

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 


/* ip_pw_sts1 register */

#define STS1_IP_SLEEP_STS	BIT(30)

#define STS1_U3_MAC_RST	BIT(16)

#define STS1_XHCI_RST		BIT(11)

#define STS1_SYS125_RST	BIT(10)

#define STS1_REF_RST		BIT(8)
@@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 
	check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |

			STS1_SYS125_RST | STS1_XHCI_RST;



	if (mtk->num_u3_ports)

		check_val |= STS1_U3_MAC_RST;



	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,

			  (check_val == (value & check_val)), 100, 20000);

	if (ret) {