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Commit cdf6d8b1 authored by Jack Pham's avatar Jack Pham
Browse files

arm: dts: msm: Update USB QMP DP PHY settings to v1.02 for sm8150 v2 



Update the USB QMP DP PHY settings to the configuration sequence
based on version 1.02 of the HPG spreadsheet.

Change-Id: I8610996bfc2e532d5403de2af519ec2455f76410
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 12165278

arch/arm64/boot/dts/qcom/sm8150-v2.dtsi

+12 −11
Original line number Diff line number Diff line
@@ -985,6 +985,7 @@ 
	     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

	     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

	     USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

	     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

	     USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

	     USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

	     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
@@ -1005,19 +1006,17 @@ 
	     USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

	     USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

	     USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

	     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

	     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

	     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

	     USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

	     USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

	     USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

	     USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x2 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

	     USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

	     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

	     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

	     USB3_DP_QSERDES_TXA_LANE_MODE_1 0xd5 0

	     USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
@@ -1025,7 +1024,7 @@ 
	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

	     USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0

	     USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

	     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2f 0

	     USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

	     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xff 0
@@ -1045,7 +1044,6 @@ 
	     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xc0 0

	     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

	     USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

	     USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

	     USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

	     USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0e 0

	     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xbf 0
@@ -1068,8 +1066,8 @@ 
	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

	     USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0

	     USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x20 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0

	     USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x01 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

	     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2f 0

	     USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0

	     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xff 0
@@ -1089,7 +1087,6 @@ 
	     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xc0 0

	     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

	     USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

	     USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

	     USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

	     USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0e 0

	     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xbf 0
@@ -1107,13 +1104,17 @@ 
	     USB3_DP_QSERDES_RXB_DCC_CTRL1 0xc 0

	     USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd0 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x17 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

	     USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

	     USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

	     USB3_DP_PCS_RX_SIGDET_LVL 0xaa 0

	     USB3_DP_PCS_CDR_RESET_TIME 0x0f 0

	     USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

	     USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

	     USB3_DP_PCS_EQ_CONFIG1 0x0d 0

	     USB3_DP_PCS_EQ_CONFIG5 0x50 0

	     USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0c 0

	     USB3_DP_PCS_EQ_CONFIG1 0x4b 0

	     USB3_DP_PCS_EQ_CONFIG5 0x10 0

	     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

	     USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

	     0xffffffff 0xffffffff 0x00>;