bnx2x: Fix line indentation (cd88ccee) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/net/bnx2x/bnx2x_link.c

+591 −635

Original line number	Original line	Diff line number	Diff line
	/* Copyright 2008-2009 Broadcom Corporation		/* Copyright 2008-2011 Broadcom Corporation
	*		*
	* Unless you and Broadcom execute a separate written software license		* Unless you and Broadcom execute a separate written software license
	* agreement governing use of this software, this software is licensed to you		* agreement governing use of this software, this software is licensed to you
	@@ -28,7 +28,8 @@

	/********************************************************/		/********************************************************/
	#define ETH_HLEN 14		#define ETH_HLEN 14
	#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */		/* L2 header size + 2VLANs (8 bytes) + LLC SNAP (8 bytes) /
			#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
	#define ETH_MIN_PACKET_SIZE 60		#define ETH_MIN_PACKET_SIZE 60
	#define ETH_MAX_PACKET_SIZE 1500		#define ETH_MAX_PACKET_SIZE 1500
	#define ETH_MAX_JUMBO_PACKET_SIZE 9600		#define ETH_MAX_JUMBO_PACKET_SIZE 9600
	@@ -329,8 +330,7 @@ void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
	if ((0 == total_bw) \|\|		if ((0 == total_bw) \|\|
	(0 == cos0_bw) \|\|		(0 == cos0_bw) \|\|
	(0 == cos1_bw)) {		(0 == cos1_bw)) {
	DP(NETIF_MSG_LINK,		DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
	"bnx2x_ets_bw_limit: Total BW can't be zero\n");
	return;		return;
	}		}

	@@ -531,8 +531,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
	if (CHIP_REV_IS_EMUL(bp)) {		if (CHIP_REV_IS_EMUL(bp)) {
	/* Use lane 1 (of lanes 0-3) */		/* Use lane 1 (of lanes 0-3) */
	REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);		REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
	port*4, 1);
	}		}
	/* for fpga */		/* for fpga */
	else		else
	@@ -542,8 +541,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
	DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");		DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");

	REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);		REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
	0);
	} else		} else
	/* ASIC */		/* ASIC */
	if (vars->phy_flags & PHY_XGXS_FLAG) {		if (vars->phy_flags & PHY_XGXS_FLAG) {
	@@ -553,17 +551,14 @@ static u8 bnx2x_emac_enable(struct link_params *params,

	DP(NETIF_MSG_LINK, "XGXS\n");		DP(NETIF_MSG_LINK, "XGXS\n");
	/* select the master lanes (out of 0-3) */		/* select the master lanes (out of 0-3) */
	REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +		REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
	port*4, ser_lane);
	/* select XGXS */		/* select XGXS */
	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
	port*4, 1);

	} else { /* SerDes */		} else { /* SerDes */
	DP(NETIF_MSG_LINK, "SerDes\n");		DP(NETIF_MSG_LINK, "SerDes\n");
	/* select SerDes */		/* select SerDes */
	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
	port*4, 0);
	}		}

	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,		bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
	@@ -574,8 +569,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
	if (CHIP_REV_IS_SLOW(bp)) {		if (CHIP_REV_IS_SLOW(bp)) {
	/* config GMII mode */		/* config GMII mode */
	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
	EMAC_WR(bp, EMAC_REG_EMAC_MODE,		EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val \| EMAC_MODE_PORT_GMII));
	(val \| EMAC_MODE_PORT_GMII));
	} else { /* ASIC */		} else { /* ASIC */
	/* pause enable/disable */		/* pause enable/disable */
	bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,		bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
	@@ -668,8 +662,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,

	if (CHIP_REV_IS_EMUL(bp)) {		if (CHIP_REV_IS_EMUL(bp)) {
	/* take the BigMac out of reset */		/* take the BigMac out of reset */
	REG_WR(bp,		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
	GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
	(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));		(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));

	/* enable access for bmac registers */		/* enable access for bmac registers */
	@@ -731,8 +724,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
	val \|= (1<<5);		val \|= (1<<5);
	wb_data[0] = val;		wb_data[0] = val;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
	wb_data, 2);
	udelay(30);		udelay(30);

	/* Tx control */		/* Tx control */
	@@ -795,8 +787,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,

	wb_data[0] = val;		wb_data[0] = val;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
	wb_data, 2);
	}		}

	static void bnx2x_update_pfc_brb(struct link_params *params,		static void bnx2x_update_pfc_brb(struct link_params *params,
	@@ -1049,8 +1040,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
	/* XGXS control */		/* XGXS control */
	wb_data[0] = 0x3c;		wb_data[0] = 0x3c;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr +		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
	BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
	wb_data, 2);		wb_data, 2);

	/* tx MAC SA */		/* tx MAC SA */
	@@ -1060,8 +1050,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
	params->mac_addr[5]);		params->mac_addr[5]);
	wb_data[1] = ((params->mac_addr[0] << 8) \|		wb_data[1] = ((params->mac_addr[0] << 8) \|
	params->mac_addr[1]);		params->mac_addr[1]);
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
	wb_data, 2);

	/* mac control */		/* mac control */
	val = 0x3;		val = 0x3;
	@@ -1071,28 +1060,24 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
	}		}
	wb_data[0] = val;		wb_data[0] = val;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
	wb_data, 2);

	/* set rx mtu */		/* set rx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
	wb_data, 2);

	bnx2x_update_pfc_bmac1(params, vars);		bnx2x_update_pfc_bmac1(params, vars);

	/* set tx mtu */		/* set tx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
	wb_data, 2);

	/* set cnt max size */		/* set cnt max size */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
	wb_data, 2);

	/* configure safc */		/* configure safc */
	wb_data[0] = 0x1000200;		wb_data[0] = 0x1000200;
	@@ -1103,8 +1088,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
	if (CHIP_REV_IS_EMUL(bp)) {		if (CHIP_REV_IS_EMUL(bp)) {
	wb_data[0] = 0xf000;		wb_data[0] = 0xf000;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp,		REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
	bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
	wb_data, 2);		wb_data, 2);
	}		}

	@@ -1126,15 +1110,13 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,

	wb_data[0] = 0;		wb_data[0] = 0;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
	wb_data, 2);
	udelay(30);		udelay(30);

	/* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */		/* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
	wb_data[0] = 0x3c;		wb_data[0] = 0x3c;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr +		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
	BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
	wb_data, 2);		wb_data, 2);

	udelay(30);		udelay(30);
	@@ -1161,21 +1143,18 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,
	/* set rx mtu */		/* set rx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
	wb_data, 2);
	udelay(30);		udelay(30);

	/* set tx mtu */		/* set tx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
	wb_data, 2);
	udelay(30);		udelay(30);
	/* set cnt max size */		/* set cnt max size */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;		wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
	wb_data[1] = 0;		wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
	wb_data, 2);
	udelay(30);		udelay(30);
	bnx2x_update_pfc_bmac2(params, vars, is_lb);		bnx2x_update_pfc_bmac2(params, vars, is_lb);

	@@ -1231,8 +1210,7 @@ static void bnx2x_update_mng(struct link_params *params, u32 link_status)

	REG_WR(bp, params->shmem_base +		REG_WR(bp, params->shmem_base +
	offsetof(struct shmem_region,		offsetof(struct shmem_region,
	port_mb[params->port].link_status),		port_mb[params->port].link_status), link_status);
	link_status);
	}		}

	static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)		static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
	@@ -1414,8 +1392,7 @@ u8 bnx2x_cl45_write(struct bnx2x bp, struct bnx2x_phy phy,
	for (i = 0; i < 50; i++) {		for (i = 0; i < 50; i++) {
	udelay(10);		udelay(10);

	tmp = REG_RD(bp, phy->mdio_ctrl +		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
	EMAC_REG_EMAC_MDIO_COMM);
	if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
	udelay(5);		udelay(5);
	break;		break;
	@@ -1576,8 +1553,7 @@ static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
	aer_val = 0x3800 + offset - 1;		aer_val = 0x3800 + offset - 1;
	else		else
	aer_val = 0x3800 + offset;		aer_val = 0x3800 + offset;
	CL45_WR_OVER_CL22(bp, phy,		CL45_WR_OVER_CL22(bp, phy, MDIO_REG_BANK_AER_BLOCK,
	MDIO_REG_BANK_AER_BLOCK,
	MDIO_AER_BLOCK_AER_REG, aer_val);		MDIO_AER_BLOCK_AER_REG, aer_val);
	}		}
	static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,		static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
	@@ -1621,8 +1597,7 @@ static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)

	bnx2x_set_serdes_access(bp, port);		bnx2x_set_serdes_access(bp, port);

	REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +		REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
	port*0x10,
	DEFAULT_PHY_DEV_ADDR);		DEFAULT_PHY_DEV_ADDR);
	}		}

	@@ -1641,8 +1616,7 @@ static void bnx2x_xgxs_deassert(struct link_params *params)
	udelay(500);		udelay(500);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);

	REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +		REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
	port*0x18, 0);
	REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,		REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
	params->phy[INT_PHY].def_md_devad);		params->phy[INT_PHY].def_md_devad);
	}		}
	@@ -2121,17 +2095,14 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,

	switch (phy->req_flow_ctrl) {		switch (phy->req_flow_ctrl) {
	case BNX2X_FLOW_CTRL_AUTO:		case BNX2X_FLOW_CTRL_AUTO:
	if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {		if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
	*ieee_fc \|=		*ieee_fc \|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;		else
	} else {
	*ieee_fc \|=		*ieee_fc \|=
	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;		MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
	}
	break;		break;
	case BNX2X_FLOW_CTRL_TX:		case BNX2X_FLOW_CTRL_TX:
	*ieee_fc \|=		*ieee_fc \|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
	break;		break;

	case BNX2X_FLOW_CTRL_RX:		case BNX2X_FLOW_CTRL_RX:
	@@ -3059,8 +3030,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
	}		}
	if ((params->num_phys == MAX_PHYS) &&		if ((params->num_phys == MAX_PHYS) &&
	(params->phy[EXT_PHY2].ver_addr != 0)) {		(params->phy[EXT_PHY2].ver_addr != 0)) {
	spirom_ver = REG_RD(bp,		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
	params->phy[EXT_PHY2].ver_addr);
	if (params->phy[EXT_PHY2].format_fw_ver) {		if (params->phy[EXT_PHY2].format_fw_ver) {
	*ver_p = '/';		*ver_p = '/';
	ver_p++;		ver_p++;
	@@ -3109,9 +3079,7 @@ static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
	bnx2x_set_aer_mmd_xgxs(params, phy);		bnx2x_set_aer_mmd_xgxs(params, phy);

	/* and md_devad */		/* and md_devad */
	REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,		REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
	md_devad);

	} else {		} else {
	u16 mii_ctrl;		u16 mii_ctrl;
	DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");		DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
	@@ -3190,20 +3158,17 @@ u8 bnx2x_set_led(struct link_params *params,
	REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);		REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
	REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);		REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
	} else {		} else {
	REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,		REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
	hw_led_mode);
	}		}

	REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +		REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
	port*4, 0);
	/* Set blinking rate to ~15.9Hz */		/* Set blinking rate to ~15.9Hz */
	REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,		REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
	LED_BLINK_RATE_VAL);		LED_BLINK_RATE_VAL);
	REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +		REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
	port*4, 1);		port*4, 1);
	tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);		tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
	EMAC_WR(bp, EMAC_REG_EMAC_LED,		EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
	(tmp & (~EMAC_LED_OVERRIDE)));

	if (CHIP_IS_E1(bp) &&		if (CHIP_IS_E1(bp) &&
	((speed == SPEED_2500) \|\|		((speed == SPEED_2500) \|\|
	@@ -3358,8 +3323,7 @@ static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
	struct link_params *params)		struct link_params *params)
	{		{
	/* reset the SerDes/XGXS */		/* reset the SerDes/XGXS */
	REG_WR(params->bp, GRCBASE_MISC +		REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
	MISC_REGISTERS_RESET_REG_3_CLEAR,
	(0x1ff << (params->port*16)));		(0x1ff << (params->port*16)));
	}		}

	@@ -3409,8 +3373,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,

	/* reset BigMac */		/* reset BigMac */
	bnx2x_bmac_rx_disable(bp, params->port);		bnx2x_bmac_rx_disable(bp, params->port);
	REG_WR(bp, GRCBASE_MISC +		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	MISC_REGISTERS_RESET_REG_2_CLEAR,
	(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));		(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
	return 0;		return 0;
	}		}
	@@ -3505,8 +3468,7 @@ u8 bnx2x_link_update(struct link_params params, struct link_vars vars)
	DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",		DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
	REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),		REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
	is_mi_int,		is_mi_int,
	REG_RD(bp,		REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
	NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));

	DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",		DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
	REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),		REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
	@@ -3658,8 +3620,8 @@ u8 bnx2x_link_update(struct link_params params, struct link_vars vars)
	ext_phy_line_speed);		ext_phy_line_speed);
	vars->phy_link_up = 0;		vars->phy_link_up = 0;
	} else if (prev_line_speed != vars->line_speed) {		} else if (prev_line_speed != vars->line_speed) {
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
	+ params->port*4, 0);		0);
	msleep(1);		msleep(1);
	}		}
	}		}
	@@ -4628,7 +4590,7 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
	return -EINVAL;		return -EINVAL;
	}		}

	static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,		u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
	struct link_params *params, u16 addr,		struct link_params *params, u16 addr,
	u8 byte_cnt, u8 *o_buf)		u8 byte_cnt, u8 *o_buf)
	{		{
	@@ -4868,8 +4830,7 @@ static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
	cur_limiting_mode);		cur_limiting_mode);

	if (edc_mode == EDC_MODE_LIMITING) {		if (edc_mode == EDC_MODE_LIMITING) {
	DP(NETIF_MSG_LINK,		DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
	"Setting LIMITING MODE\n");
	bnx2x_cl45_write(bp, phy,		bnx2x_cl45_write(bp, phy,
	MDIO_PMA_DEVAD,		MDIO_PMA_DEVAD,
	MDIO_PMA_REG_ROM_VER2,		MDIO_PMA_REG_ROM_VER2,
	@@ -4976,8 +4937,7 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
	if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {		if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
	DP(NETIF_MSG_LINK, "Failed to get valid module type\n");		DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
	return -EINVAL;		return -EINVAL;
	} else if (bnx2x_verify_sfp_module(phy, params) !=		} else if (bnx2x_verify_sfp_module(phy, params) != 0) {
	0) {
	/* check SFP+ module compatibility */		/* check SFP+ module compatibility */
	DP(NETIF_MSG_LINK, "Module verification failed!!\n");		DP(NETIF_MSG_LINK, "Module verification failed!!\n");
	rc = -EINVAL;		rc = -EINVAL;
	@@ -7253,14 +7213,16 @@ static void bnx2x_phy_def_cfg(struct link_params *params,
	offsetof(struct shmem_region, dev_info.		offsetof(struct shmem_region, dev_info.
	port_feature_config[params->port].link_config2));		port_feature_config[params->port].link_config2));
	phy->speed_cap_mask = REG_RD(bp, params->shmem_base +		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
	offsetof(struct shmem_region, dev_info.		offsetof(struct shmem_region,
			dev_info.
	port_hw_config[params->port].speed_capability_mask2));		port_hw_config[params->port].speed_capability_mask2));
	} else {		} else {
	link_config = REG_RD(bp, params->shmem_base +		link_config = REG_RD(bp, params->shmem_base +
	offsetof(struct shmem_region, dev_info.		offsetof(struct shmem_region, dev_info.
	port_feature_config[params->port].link_config));		port_feature_config[params->port].link_config));
	phy->speed_cap_mask = REG_RD(bp, params->shmem_base +		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
	offsetof(struct shmem_region, dev_info.		offsetof(struct shmem_region,
			dev_info.
	port_hw_config[params->port].speed_capability_mask));		port_hw_config[params->port].speed_capability_mask));
	}		}
	DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"		DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
	@@ -7527,8 +7489,7 @@ u8 bnx2x_phy_init(struct link_params params, struct link_vars vars)
	/* set bmac loopback */		/* set bmac loopback */
	bnx2x_bmac_enable(params, vars, 1);		bnx2x_bmac_enable(params, vars, 1);

	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
	params->port*4, 0);

	} else if (params->loopback_mode == LOOPBACK_EMAC) {		} else if (params->loopback_mode == LOOPBACK_EMAC) {

	@@ -7544,8 +7505,7 @@ u8 bnx2x_phy_init(struct link_params params, struct link_vars vars)
	/* set bmac loopback */		/* set bmac loopback */
	bnx2x_emac_enable(params, vars, 1);		bnx2x_emac_enable(params, vars, 1);
	bnx2x_emac_program(params, vars);		bnx2x_emac_program(params, vars);
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
	params->port*4, 0);

	} else if ((params->loopback_mode == LOOPBACK_XGXS) \|\|		} else if ((params->loopback_mode == LOOPBACK_XGXS) \|\|
	(params->loopback_mode == LOOPBACK_EXT_PHY)) {		(params->loopback_mode == LOOPBACK_EXT_PHY)) {
	@@ -7569,7 +7529,6 @@ u8 bnx2x_phy_init(struct link_params params, struct link_vars vars)
	bnx2x_emac_enable(params, vars, 0);		bnx2x_emac_enable(params, vars, 0);
	} else		} else
	bnx2x_bmac_enable(params, vars, 0);		bnx2x_bmac_enable(params, vars, 0);

	if (params->loopback_mode == LOOPBACK_XGXS) {		if (params->loopback_mode == LOOPBACK_XGXS) {
	/* set 10G XGXS loopback */		/* set 10G XGXS loopback */
	params->phy[INT_PHY].config_loopback(		params->phy[INT_PHY].config_loopback(
	@@ -7587,9 +7546,7 @@ u8 bnx2x_phy_init(struct link_params params, struct link_vars vars)
	params);		params);
	}		}
	}		}
			REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
	params->port*4, 0);

	bnx2x_set_led(params, vars,		bnx2x_set_led(params, vars,
	LED_MODE_OPER, vars->line_speed);		LED_MODE_OPER, vars->line_speed);
	@@ -7727,7 +7684,8 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
	/* Need to take the phy out of low power mode in order		/* Need to take the phy out of low power mode in order
	to write to access its registers */		to write to access its registers */
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
	MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);		MISC_REGISTERS_GPIO_OUTPUT_HIGH,
			port);

	/* Reset the phy */		/* Reset the phy */
	bnx2x_cl45_write(bp, &phy[port],		bnx2x_cl45_write(bp, &phy[port],
	@@ -7907,9 +7865,7 @@ static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,

	/* Reset the phy */		/* Reset the phy */
	bnx2x_cl45_write(bp, &phy[port],		bnx2x_cl45_write(bp, &phy[port],
	MDIO_PMA_DEVAD,		MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
	MDIO_PMA_REG_CTRL,
	1<<15);
	}		}

	/* Add delay of 150ms after reset */		/* Add delay of 150ms after reset */

drivers/net/bnx2x/bnx2x_link.h

+16 −13

Original line number	Original line	Diff line number	Diff line
	/* Copyright 2008-2010 Broadcom Corporation		/* Copyright 2008-2011 Broadcom Corporation
	*		*
	* Unless you and Broadcom execute a separate written software license		* Unless you and Broadcom execute a separate written software license
	* agreement governing use of this software, this software is licensed to you		* agreement governing use of this software, this software is licensed to you
	@@ -207,6 +207,8 @@ struct link_params {
	#define LOOPBACK_XGXS 3		#define LOOPBACK_XGXS 3
	#define LOOPBACK_EXT_PHY 4		#define LOOPBACK_EXT_PHY 4
	#define LOOPBACK_EXT 5		#define LOOPBACK_EXT 5
			#define LOOPBACK_UMAC 6
			#define LOOPBACK_XMAC 7

	/* Device parameters */		/* Device parameters */
	u8 mac_addr[6];		u8 mac_addr[6];
	@@ -230,6 +232,7 @@ struct link_params {
	/* Phy register parameter */		/* Phy register parameter */
	u32 chip_id;		u32 chip_id;

			/* features */
	u32 feature_config_flags;		u32 feature_config_flags;
	#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)		#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
	#define FEATURE_CONFIG_PFC_ENABLED (1<<1)		#define FEATURE_CONFIG_PFC_ENABLED (1<<1)