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Commit cd1f11de authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs 



perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with
the same value. Add a little optimization to skip the unnecessary
write.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 1a78d937

arch/x86/kernel/cpu/perf_event_intel_lbr.c

+4 −2
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); 
static void __intel_pmu_lbr_enable(bool pmi)

{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	u64 debugctl, lbr_select = 0;

	u64 debugctl, lbr_select = 0, orig_debugctl;



	/*

	 * No need to reprogram LBR_SELECT in a PMI, as it
@@ -147,6 +147,7 @@ static void __intel_pmu_lbr_enable(bool pmi) 
	}



	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);

	orig_debugctl = debugctl;

	debugctl |= DEBUGCTLMSR_LBR;

	/*

	 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
@@ -155,6 +156,7 @@ static void __intel_pmu_lbr_enable(bool pmi) 
	 */

	if (!(lbr_select & LBR_CALL_STACK))

		debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;

	if (orig_debugctl != debugctl)

		wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);

}