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Commit ccf010fb authored by Maarten Lankhorst's avatar Maarten Lankhorst
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drm/i915: Add an atomic evasion step to watermark programming, v4. 



Allow the driver to write watermarks during atomic evasion.
This will make it possible to write the watermarks in a cleaner
way on gen9+.

intel_atomic_state is not used here yet, but will be used when
we program all watermarks as a separate step during evasion.

This also writes linetime all the time, while before it was only
done during plane updates. This looks like this could be a bugfix,
but I'm not sure what it affects.

Changes since v1:
- Add comment about atomic evasion to commit message.
- Unwrap I915_WRITE call. (Lyude)
Changes since v2:
- Rename atomic_evade_watermarks to atomic_update_watermarks. (Ville)
- Add line wraps where appropriate, fix grammar in commit message. (Matt)
Changes since v3:
- Actually fix commit message. (Matt)
- Line wrap calls to watermark update functions. (Matt)

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478609742-13603-2-git-send-email-maarten.lankhorst@linux.intel.com
parent 9a151987

drivers/gpu/drm/i915/i915_drv.h

+7 −2
Original line number Original line Diff line number Diff line
@@ -474,6 +474,7 @@ struct sdvo_device_mapping { 




struct intel_connector;

struct intel_connector;

struct intel_encoder;

struct intel_encoder;

struct intel_atomic_state;

struct intel_crtc_state;

struct intel_crtc_state;

struct intel_initial_plane_config;

struct intel_initial_plane_config;

struct intel_crtc;

struct intel_crtc;
@@ -487,8 +488,12 @@ struct drm_i915_display_funcs { 
	int (*compute_intermediate_wm)(struct drm_device *dev,

	int (*compute_intermediate_wm)(struct drm_device *dev,

				       struct intel_crtc *intel_crtc,

				       struct intel_crtc *intel_crtc,

				       struct intel_crtc_state *newstate);

				       struct intel_crtc_state *newstate);

	void (*initial_watermarks)(struct intel_crtc_state *cstate);

	void (*initial_watermarks)(struct intel_atomic_state *state,

	void (*optimize_watermarks)(struct intel_crtc_state *cstate);

				   struct intel_crtc_state *cstate);

	void (*atomic_update_watermarks)(struct intel_atomic_state *state,

					 struct intel_crtc_state *cstate);

	void (*optimize_watermarks)(struct intel_atomic_state *state,

				    struct intel_crtc_state *cstate);

	int (*compute_global_watermarks)(struct drm_atomic_state *state);

	int (*compute_global_watermarks)(struct drm_atomic_state *state);

	void (*update_wm)(struct intel_crtc *crtc);

	void (*update_wm)(struct intel_crtc *crtc);

	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);

	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);

drivers/gpu/drm/i915/intel_display.c

+27 −14
Original line number Original line Diff line number Diff line
@@ -5111,6 +5111,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) 
	struct drm_plane_state *old_pri_state =

	struct drm_plane_state *old_pri_state =

		drm_atomic_get_existing_plane_state(old_state, primary);

		drm_atomic_get_existing_plane_state(old_state, primary);

	bool modeset = needs_modeset(&pipe_config->base);

	bool modeset = needs_modeset(&pipe_config->base);

	struct intel_atomic_state *old_intel_state =

		to_intel_atomic_state(old_state);





	if (old_pri_state) {

	if (old_pri_state) {

		struct intel_plane_state *primary_state =

		struct intel_plane_state *primary_state =
@@ -5178,7 +5180,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) 
	 * us to.

	 * us to.

	 */

	 */

	if (dev_priv->display.initial_watermarks != NULL)

	if (dev_priv->display.initial_watermarks != NULL)

		dev_priv->display.initial_watermarks(pipe_config);

		dev_priv->display.initial_watermarks(old_intel_state,

						     pipe_config);

	else if (pipe_config->update_wm_pre)

	else if (pipe_config->update_wm_pre)

		intel_update_watermarks(crtc);

		intel_update_watermarks(crtc);

}

}
@@ -5334,6 +5337,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	int pipe = intel_crtc->pipe;

	struct intel_atomic_state *old_intel_state =

		to_intel_atomic_state(old_state);





	if (WARN_ON(intel_crtc->active))

	if (WARN_ON(intel_crtc->active))

		return;

		return;
@@ -5392,7 +5397,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, 
	intel_color_load_luts(&pipe_config->base);

	intel_color_load_luts(&pipe_config->base);





	if (dev_priv->display.initial_watermarks != NULL)

	if (dev_priv->display.initial_watermarks != NULL)

		dev_priv->display.initial_watermarks(intel_crtc->config);

		dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);

	intel_enable_pipe(intel_crtc);

	intel_enable_pipe(intel_crtc);





	if (intel_crtc->config->has_pch_encoder)

	if (intel_crtc->config->has_pch_encoder)
@@ -5428,6 +5433,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe, hsw_workaround_pipe;

	int pipe = intel_crtc->pipe, hsw_workaround_pipe;

	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;

	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;

	struct intel_atomic_state *old_intel_state =

		to_intel_atomic_state(old_state);





	if (WARN_ON(intel_crtc->active))

	if (WARN_ON(intel_crtc->active))

		return;

		return;
@@ -5498,7 +5505,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 
		intel_ddi_enable_transcoder_func(crtc);

		intel_ddi_enable_transcoder_func(crtc);





	if (dev_priv->display.initial_watermarks != NULL)

	if (dev_priv->display.initial_watermarks != NULL)

		dev_priv->display.initial_watermarks(pipe_config);

		dev_priv->display.initial_watermarks(old_intel_state,

						     pipe_config);

	else

	else

		intel_update_watermarks(intel_crtc);

		intel_update_watermarks(intel_crtc);
@@ -14484,7 +14492,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) 
		intel_cstate = to_intel_crtc_state(crtc->state);

		intel_cstate = to_intel_crtc_state(crtc->state);





		if (dev_priv->display.optimize_watermarks)

		if (dev_priv->display.optimize_watermarks)

			dev_priv->display.optimize_watermarks(intel_cstate);

			dev_priv->display.optimize_watermarks(intel_state,

							      intel_cstate);

	}

	}





	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {

	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
@@ -14927,10 +14936,11 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, 
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc_state *intel_cstate =

	struct intel_crtc_state *intel_cstate =

		to_intel_crtc_state(crtc->state);

		to_intel_crtc_state(crtc->state);

	struct intel_crtc_state *old_intel_state =

	struct intel_crtc_state *old_intel_cstate =

		to_intel_crtc_state(old_crtc_state);

		to_intel_crtc_state(old_crtc_state);

	struct intel_atomic_state *old_intel_state =

		to_intel_atomic_state(old_crtc_state->state);

	bool modeset = needs_modeset(crtc->state);

	bool modeset = needs_modeset(crtc->state);

	enum pipe pipe = intel_crtc->pipe;





	/* Perform vblank evasion around commit operation */

	/* Perform vblank evasion around commit operation */

	intel_pipe_update_start(intel_crtc);

	intel_pipe_update_start(intel_crtc);
@@ -14943,14 +14953,14 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, 
		intel_color_load_luts(crtc->state);

		intel_color_load_luts(crtc->state);

	}

	}





	if (intel_cstate->update_pipe) {

	if (intel_cstate->update_pipe)

		intel_update_pipe_config(intel_crtc, old_intel_state);

		intel_update_pipe_config(intel_crtc, old_intel_cstate);

	} else if (INTEL_GEN(dev_priv) >= 9) {

	else if (INTEL_GEN(dev_priv) >= 9)

		skl_detach_scalers(intel_crtc);

		skl_detach_scalers(intel_crtc);





		I915_WRITE(PIPE_WM_LINETIME(pipe),

	if (dev_priv->display.atomic_update_watermarks)

			   intel_cstate->wm.skl.optimal.linetime);

		dev_priv->display.atomic_update_watermarks(old_intel_state,

	}

							   intel_cstate);

}

}





static void intel_finish_crtc_commit(struct drm_crtc *crtc,

static void intel_finish_crtc_commit(struct drm_crtc *crtc,
@@ -16373,6 +16383,7 @@ static void sanitize_watermarks(struct drm_device *dev) 
{

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_atomic_state *state;

	struct drm_atomic_state *state;

	struct intel_atomic_state *intel_state;

	struct drm_crtc *crtc;

	struct drm_crtc *crtc;

	struct drm_crtc_state *cstate;

	struct drm_crtc_state *cstate;

	struct drm_modeset_acquire_ctx ctx;

	struct drm_modeset_acquire_ctx ctx;
@@ -16401,12 +16412,14 @@ static void sanitize_watermarks(struct drm_device *dev) 
	if (WARN_ON(IS_ERR(state)))

	if (WARN_ON(IS_ERR(state)))

		goto fail;

		goto fail;





	intel_state = to_intel_atomic_state(state);



	/*

	/*

	 * Hardware readout is the only time we don't want to calculate

	 * Hardware readout is the only time we don't want to calculate

	 * intermediate watermarks (since we don't trust the current

	 * intermediate watermarks (since we don't trust the current

	 * watermarks).

	 * watermarks).

	 */

	 */

	to_intel_atomic_state(state)->skip_intermediate_wm = true;

	intel_state->skip_intermediate_wm = true;





	ret = intel_atomic_check(dev, state);

	ret = intel_atomic_check(dev, state);

	if (ret) {

	if (ret) {
@@ -16430,7 +16443,7 @@ static void sanitize_watermarks(struct drm_device *dev) 
		struct intel_crtc_state *cs = to_intel_crtc_state(cstate);

		struct intel_crtc_state *cs = to_intel_crtc_state(cstate);





		cs->wm.need_postvbl_update = true;

		cs->wm.need_postvbl_update = true;

		dev_priv->display.optimize_watermarks(cs);

		dev_priv->display.optimize_watermarks(intel_state, cs);

	}

	}





put_state:

put_state:

drivers/gpu/drm/i915/intel_pm.c

+16 −2
Original line number Original line Diff line number Diff line
@@ -4196,6 +4196,17 @@ skl_compute_wm(struct drm_atomic_state *state) 
	return 0;

	return 0;

}

}





static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,

				      struct intel_crtc_state *cstate)

{

	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;

	enum pipe pipe = crtc->pipe;



	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);

}



static void skl_update_wm(struct intel_crtc *intel_crtc)

static void skl_update_wm(struct intel_crtc *intel_crtc)

{

{

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_device *dev = intel_crtc->base.dev;
@@ -4286,7 +4297,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) 
	ilk_write_wm_values(dev_priv, &results);

	ilk_write_wm_values(dev_priv, &results);

}

}





static void ilk_initial_watermarks(struct intel_crtc_state *cstate)

static void ilk_initial_watermarks(struct intel_atomic_state *state,

				   struct intel_crtc_state *cstate)

{

{

	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
@@ -4297,7 +4309,8 @@ static void ilk_initial_watermarks(struct intel_crtc_state *cstate) 
	mutex_unlock(&dev_priv->wm.wm_mutex);

	mutex_unlock(&dev_priv->wm.wm_mutex);

}

}





static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)

static void ilk_optimize_watermarks(struct intel_atomic_state *state,

				    struct intel_crtc_state *cstate)

{

{

	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
@@ -7694,6 +7707,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
	if (INTEL_GEN(dev_priv) >= 9) {

	if (INTEL_GEN(dev_priv) >= 9) {

		skl_setup_wm_latency(dev_priv);

		skl_setup_wm_latency(dev_priv);

		dev_priv->display.update_wm = skl_update_wm;

		dev_priv->display.update_wm = skl_update_wm;

		dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;

		dev_priv->display.compute_global_watermarks = skl_compute_wm;

		dev_priv->display.compute_global_watermarks = skl_compute_wm;

	} else if (HAS_PCH_SPLIT(dev_priv)) {

	} else if (HAS_PCH_SPLIT(dev_priv)) {

		ilk_setup_wm_latency(dev_priv);

		ilk_setup_wm_latency(dev_priv);