Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cc67ae90 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent 



On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-6-wens@csie.org
parent 4b1c924b

drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c

+29 −24
Original line number Diff line number Diff line
@@ -67,11 +67,11 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long rate, 
static int sun4i_tmds_determine_rate(struct clk_hw *hw,

				     struct clk_rate_request *req)

{

	struct clk_hw *parent;

	struct clk_hw *parent = NULL;

	unsigned long best_parent = 0;

	unsigned long rate = req->rate;

	int best_div = 1, best_half = 1;

	int i, j;

	int i, j, p;



	/*

	 * We only consider PLL3, since the TCON is very likely to be
@@ -79,9 +79,10 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw, 
	 * clock, so we should not need to do anything.

	 */



	parent = clk_hw_get_parent_by_index(hw, 0);

	for (p = 0; p < clk_hw_get_num_parents(hw); p++) {

		parent = clk_hw_get_parent_by_index(hw, p);

		if (!parent)

		return -EINVAL;

			continue;



		for (i = 1; i < 3; i++) {

			for (j = 1; j < 16; j++) {
@@ -104,6 +105,10 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw, 
				}

			}

		}

	}



	if (!parent)

		return -EINVAL;



out:

	req->rate = best_parent / best_half / best_div;