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Commit cbe2bb4f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/misc' into next 

* pci/misc:
  PCI: Fix comment typo for pci_add_cap_save_buffer()
  PCI: Return -ENOSYS for SR-IOV operations on non-SR-IOV devices
  PCI: Update NumVFs register when disabling SR-IOV
  x86/PCI: MMCONFIG: Check earlier for MMCONFIG region at address zero
  PCI: Convert class code to use dev_groups
  frv/PCI: Mark pcibios_fixup_bus() as non-init
  x86/pci/mrst: Cleanup checkpatch.pl warnings
  PCI: Rename "PCI Express support" kconfig title
  PCI: Fix comment typo in iov.c
parents 28fa60a8 ce1be10b

arch/frv/mb93090-mb00/pci-vdk.c

+1 −1
Original line number Diff line number Diff line
@@ -320,7 +320,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 
 *  are examined.

 */



void __init pcibios_fixup_bus(struct pci_bus *bus)

void pcibios_fixup_bus(struct pci_bus *bus)

{

#if 0

	printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);

arch/x86/pci/mmconfig-shared.c

+1 −6
Original line number Diff line number Diff line
@@ -700,7 +700,7 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, 
	if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)

		return -ENODEV;



	if (start > end)

	if (start > end || !addr)

		return -EINVAL;



	mutex_lock(&pci_mmcfg_lock);
@@ -716,11 +716,6 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, 
		return -EEXIST;

	}



	if (!addr) {

		mutex_unlock(&pci_mmcfg_lock);

		return -EINVAL;

	}



	rc = -EBUSY;

	cfg = pci_mmconfig_alloc(seg, start, end, addr);

	if (cfg == NULL) {

arch/x86/pci/mrst.c

+24 −17
Original line number Diff line number Diff line
@@ -23,11 +23,11 @@ 
#include <linux/ioport.h>

#include <linux/init.h>

#include <linux/dmi.h>

#include <linux/acpi.h>

#include <linux/io.h>

#include <linux/smp.h>



#include <asm/acpi.h>

#include <asm/segment.h>

#include <asm/io.h>

#include <asm/smp.h>

#include <asm/pci_x86.h>

#include <asm/hw_irq.h>

#include <asm/io_apic.h>
@@ -43,7 +43,7 @@ 
#define PCI_FIXED_BAR_4_SIZE	0x14

#define PCI_FIXED_BAR_5_SIZE	0x1c



static int pci_soc_mode = 0;

static int pci_soc_mode;



/**

 * fixed_bar_cap - return the offset of the fixed BAR cap if found
@@ -141,7 +141,8 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, 
 */

static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)

{

	/* This is a workaround for A0 LNC bug where PCI status register does

	/*

	 * This is a workaround for A0 LNC bug where PCI status register does

	 * not have new CAP bit set. can not be written by SW either.

	 *

	 * PCI header type in real LNC indicates a single function device, this
@@ -154,7 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) 
				|| devfn == PCI_DEVFN(0, 0)

				|| devfn == PCI_DEVFN(3, 0)))

		return 1;

	return 0; /* langwell on others */

	return 0; /* Langwell on others */

}



static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
@@ -172,7 +173,8 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, 
{

	int offset;



	/* On MRST, there is no PCI ROM BAR, this will cause a subsequent read

	/*

	 * On MRST, there is no PCI ROM BAR, this will cause a subsequent read

	 * to ROM BAR return 0 then being ignored.

	 */

	if (where == PCI_ROM_ADDRESS)
@@ -210,7 +212,8 @@ static int mrst_pci_irq_enable(struct pci_dev *dev) 


	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);



	/* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to

	/*

	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to

	 * IOAPIC RTE entries, so we just enable RTE for the device.

	 */

	irq_attr.ioapic = mp_find_ioapic(dev->irq);
@@ -235,7 +238,7 @@ struct pci_ops pci_mrst_ops = { 
 */

int __init pci_mrst_init(void)

{

	printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");

	pr_info("Intel MID platform detected, using MID PCI ops\n");

	pci_mmcfg_late_init();

	pcibios_enable_irq = mrst_pci_irq_enable;

	pci_root_ops = pci_mrst_ops;
@@ -244,17 +247,21 @@ int __init pci_mrst_init(void) 
	return 1;

}



/* Langwell devices are not true pci devices, they are not subject to 10 ms

 * d3 to d0 delay required by pci spec.

/*

 * Langwell devices are not true PCI devices; they are not subject to 10 ms

 * d3 to d0 delay required by PCI spec.

 */

static void pci_d3delay_fixup(struct pci_dev *dev)

{

	/* PCI fixups are effectively decided compile time. If we have a dual

	   SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */

	/*

	 * PCI fixups are effectively decided compile time. If we have a dual

	 * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.

	 */

	if (!pci_soc_mode)

		return;

	/* true pci devices in lincroft should allow type 1 access, the rest

	 * are langwell fake pci devices.

	/*

	 * True PCI devices in Lincroft should allow type 1 access, the rest

	 * are Langwell fake PCI devices.

	 */

	if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))

		return;

drivers/pci/iov.c

+14 −9
Original line number Diff line number Diff line
@@ -286,7 +286,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 
	    (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))

		return -EINVAL;



	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);

	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);

	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);

	if (!offset || (nr_virtfn > 1 && !stride))
@@ -324,7 +323,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 


		if (!pdev->is_physfn) {

			pci_dev_put(pdev);

			return -ENODEV;

			return -ENOSYS;

		}



		rc = sysfs_create_link(&dev->dev.kobj,
@@ -334,6 +333,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 
			return rc;

	}



	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);

	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;

	pci_cfg_access_lock(dev);

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
@@ -368,6 +368,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) 
	iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);

	pci_cfg_access_lock(dev);

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);

	ssleep(1);

	pci_cfg_access_unlock(dev);
@@ -401,6 +402,7 @@ static void sriov_disable(struct pci_dev *dev) 
		sysfs_remove_link(&dev->dev.kobj, "dep_link");



	iov->num_VFs = 0;

	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);

}



static int sriov_init(struct pci_dev *dev, int pos)
@@ -662,7 +664,7 @@ int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 
	might_sleep();



	if (!dev->is_physfn)

		return -ENODEV;

		return -ENOSYS;



	return sriov_enable(dev, nr_virtfn);

}
@@ -722,7 +724,7 @@ EXPORT_SYMBOL_GPL(pci_num_vf); 
 * @dev: the PCI device

 *

 * Returns number of VFs belonging to this device that are assigned to a guest.

 * If device is not a physical function returns -ENODEV.

 * If device is not a physical function returns 0.

 */

int pci_vfs_assigned(struct pci_dev *dev)

{
@@ -767,12 +769,15 @@ EXPORT_SYMBOL_GPL(pci_vfs_assigned); 
 * device's mutex held.

 *

 * Returns 0 if PF is an SRIOV-capable device and

 * value of numvfs valid. If not a PF with VFS, return -EINVAL;

 * value of numvfs valid. If not a PF return -ENOSYS;

 * if numvfs is invalid return -EINVAL;

 * if VFs already enabled, return -EBUSY.

 */

int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)

{

	if (!dev->is_physfn || (numvfs > dev->sriov->total_VFs))

	if (!dev->is_physfn)

		return -ENOSYS;

	if (numvfs > dev->sriov->total_VFs)

		return -EINVAL;



	/* Shouldn't change if VFs already enabled */
@@ -786,17 +791,17 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 
EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs);



/**

 * pci_sriov_get_totalvfs -- get total VFs supported on this devic3

 * pci_sriov_get_totalvfs -- get total VFs supported on this device

 * @dev: the PCI PF device

 *

 * For a PCIe device with SRIOV support, return the PCIe

 * SRIOV capability value of TotalVFs or the value of driver_max_VFs

 * if the driver reduced it.  Otherwise, -EINVAL.

 * if the driver reduced it.  Otherwise 0.

 */

int pci_sriov_get_totalvfs(struct pci_dev *dev)

{

	if (!dev->is_physfn)

		return -EINVAL;

		return 0;



	if (dev->sriov->driver_max_VFs)

		return dev->sriov->driver_max_VFs;

drivers/pci/pci-sysfs.c

+21 −11
Original line number Diff line number Diff line
@@ -131,19 +131,19 @@ static ssize_t pci_bus_show_cpuaffinity(struct device *dev, 
	return ret;

}



static inline ssize_t pci_bus_show_cpumaskaffinity(struct device *dev,

					struct device_attribute *attr,

					char *buf)

static ssize_t cpuaffinity_show(struct device *dev,

				struct device_attribute *attr, char *buf)

{

	return pci_bus_show_cpuaffinity(dev, 0, attr, buf);

}

static DEVICE_ATTR_RO(cpuaffinity);



static inline ssize_t pci_bus_show_cpulistaffinity(struct device *dev,

					struct device_attribute *attr,

					char *buf)

static ssize_t cpulistaffinity_show(struct device *dev,

				    struct device_attribute *attr, char *buf)

{

	return pci_bus_show_cpuaffinity(dev, 1, attr, buf);

}

static DEVICE_ATTR_RO(cpulistaffinity);



/* show resources */

static ssize_t
@@ -379,6 +379,7 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr, 
	}

	return count;

}

static DEVICE_ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store);



#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)

static ssize_t d3cold_allowed_store(struct device *dev,
@@ -514,11 +515,20 @@ struct device_attribute pci_dev_attrs[] = { 
	__ATTR_NULL,

};



struct device_attribute pcibus_dev_attrs[] = {

	__ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store),

	__ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL),

	__ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL),

	__ATTR_NULL,

static struct attribute *pcibus_attrs[] = {

	&dev_attr_rescan.attr,

	&dev_attr_cpuaffinity.attr,

	&dev_attr_cpulistaffinity.attr,

	NULL,

};



static const struct attribute_group pcibus_group = {

	.attrs = pcibus_attrs,

};



const struct attribute_group *pcibus_groups[] = {

	&pcibus_group,

	NULL,

};



static ssize_t