Loading Documentation/devicetree/bindings/arm/coresight.txt +4 −4 Original line number Diff line number Diff line Loading @@ -102,6 +102,10 @@ its hardware characteristcs. * Optional properties for all components: * reg-names: names corresponding to each reg property value. * qcom,proxy-regs: List of regulators required. * qcom,proxy-clks: List of additional clocks required. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management Loading Loading @@ -165,10 +169,6 @@ its hardware characteristcs. * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed after enabling the subunit. * qcom,tpdm-clks: List of additional clocks required. * qcom,tpdm-regs: List of regulators required. * qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms are not enabled in secure device. Loading drivers/hwtracing/coresight/coresight-tpdm.c +118 −163 File changed.Preview size limit exceeded, changes collapsed. Show changes drivers/hwtracing/coresight/coresight.c +5 −4 Original line number Diff line number Diff line Loading @@ -112,14 +112,14 @@ static void coresight_reset_all_sink(void) bus_for_each_dev(&coresight_bustype, NULL, NULL, coresight_reset_sink); } void coresight_enable_reg_clk(struct coresight_device *csdev) int coresight_enable_reg_clk(struct coresight_device *csdev) { struct coresight_reg_clk *reg_clk = csdev->reg_clk; int ret; int i, j; if (IS_ERR_OR_NULL(reg_clk)) return; return -EINVAL; for (i = 0; i < reg_clk->nr_reg; i++) { ret = regulator_enable(reg_clk->reg[i]); Loading @@ -133,14 +133,15 @@ void coresight_enable_reg_clk(struct coresight_device *csdev) goto err_clks; } return; return 0; err_clks: for (j--; j >= 0; j--) clk_disable_unprepare(reg_clk->clk[j]); err_regs: for (i--; i >= 0; i--) regulator_disable(reg_clk->reg[i]); return ret; } EXPORT_SYMBOL(coresight_enable_reg_clk); Loading include/linux/coresight.h +2 −2 Original line number Diff line number Diff line Loading @@ -298,7 +298,7 @@ extern int coresight_timeout(void __iomem *addr, u32 offset, int position, int value); extern void coresight_abort(void); extern void coresight_disable_reg_clk(struct coresight_device *csdev); extern void coresight_enable_reg_clk(struct coresight_device *csdev); extern int coresight_enable_reg_clk(struct coresight_device *csdev); #else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } Loading @@ -310,7 +310,7 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) { return 1; } static inline void coresight_abort(void) {} static inline void coresight_disable_reg_clk(struct coresight_device *csdev) {} static inline void coresight_enable_reg_clk(struct coresight_device *csdev) {} static inline int coresight_enable_reg_clk(struct coresight_device *csdev) {} #endif #ifdef CONFIG_OF Loading Loading
Documentation/devicetree/bindings/arm/coresight.txt +4 −4 Original line number Diff line number Diff line Loading @@ -102,6 +102,10 @@ its hardware characteristcs. * Optional properties for all components: * reg-names: names corresponding to each reg property value. * qcom,proxy-regs: List of regulators required. * qcom,proxy-clks: List of additional clocks required. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management Loading Loading @@ -165,10 +169,6 @@ its hardware characteristcs. * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed after enabling the subunit. * qcom,tpdm-clks: List of additional clocks required. * qcom,tpdm-regs: List of regulators required. * qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms are not enabled in secure device. Loading
drivers/hwtracing/coresight/coresight-tpdm.c +118 −163 File changed.Preview size limit exceeded, changes collapsed. Show changes
drivers/hwtracing/coresight/coresight.c +5 −4 Original line number Diff line number Diff line Loading @@ -112,14 +112,14 @@ static void coresight_reset_all_sink(void) bus_for_each_dev(&coresight_bustype, NULL, NULL, coresight_reset_sink); } void coresight_enable_reg_clk(struct coresight_device *csdev) int coresight_enable_reg_clk(struct coresight_device *csdev) { struct coresight_reg_clk *reg_clk = csdev->reg_clk; int ret; int i, j; if (IS_ERR_OR_NULL(reg_clk)) return; return -EINVAL; for (i = 0; i < reg_clk->nr_reg; i++) { ret = regulator_enable(reg_clk->reg[i]); Loading @@ -133,14 +133,15 @@ void coresight_enable_reg_clk(struct coresight_device *csdev) goto err_clks; } return; return 0; err_clks: for (j--; j >= 0; j--) clk_disable_unprepare(reg_clk->clk[j]); err_regs: for (i--; i >= 0; i--) regulator_disable(reg_clk->reg[i]); return ret; } EXPORT_SYMBOL(coresight_enable_reg_clk); Loading
include/linux/coresight.h +2 −2 Original line number Diff line number Diff line Loading @@ -298,7 +298,7 @@ extern int coresight_timeout(void __iomem *addr, u32 offset, int position, int value); extern void coresight_abort(void); extern void coresight_disable_reg_clk(struct coresight_device *csdev); extern void coresight_enable_reg_clk(struct coresight_device *csdev); extern int coresight_enable_reg_clk(struct coresight_device *csdev); #else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } Loading @@ -310,7 +310,7 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) { return 1; } static inline void coresight_abort(void) {} static inline void coresight_disable_reg_clk(struct coresight_device *csdev) {} static inline void coresight_enable_reg_clk(struct coresight_device *csdev) {} static inline int coresight_enable_reg_clk(struct coresight_device *csdev) {} #endif #ifdef CONFIG_OF Loading