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Commit ca9b6f1b authored by Xiaowen Wu's avatar Xiaowen Wu
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drm/msm/dsi-staging: add force_clk_lane_hs support 



Some panel / bridge require clock lane always in high speed mode,
this change added options in DT file to force DSI controller and
PHY output clock lane in high speed mode.

CRs-Fixed: 2242680
Change-Id: I5e69b942ef9bc77dd7a6542f37f4f41a45ffefea
Signed-off-by: default avatarXiaowen Wu <wxiaowen@codeaurora.org>
parent 9956996a
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