Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ca6ad025 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Shuffle sprite register writes into a tighter group 



Group the sprite register writes a bit tighter. We want to write
the registers atomically, and so doing the base address/offset
artihmetic within the critical section is pointless when it can
all be done beforehand.

Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 754970ee

drivers/gpu/drm/i915/intel_sprite.c

+9 −9
Original line number Diff line number Diff line
@@ -124,9 +124,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 
	crtc_w--;

	crtc_h--;



	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);

	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,

							obj->tiling_mode,
@@ -134,6 +131,9 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 
							fb->pitches[0]);

	linear_offset -= sprsurf_offset;



	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);

	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);



	if (obj->tiling_mode != I915_TILING_NONE)

		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);

	else
@@ -293,15 +293,15 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	if (crtc_w != src_w || crtc_h != src_h)

		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;



	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	sprsurf_offset =

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       pixel_size, fb->pitches[0]);

	linear_offset -= sprsurf_offset;



	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);



	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET

	 * register */

	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -472,15 +472,15 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	if (crtc_w != src_w || crtc_h != src_h)

		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;



	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	dvssurf_offset =

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       pixel_size, fb->pitches[0]);

	linear_offset -= dvssurf_offset;



	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);

	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);



	if (obj->tiling_mode != I915_TILING_NONE)

		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);

	else