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Commit c9b59da1 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge commit 'kumar/kumar-mmu'

parents 9f5494b7 4ee7084e

arch/powerpc/include/asm/highmem.h

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro 
#ifdef CONFIG_DEBUG_HIGHMEM

	BUG_ON(!pte_none(*(kmap_pte-idx)));

#endif

	set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));

	__set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));

	flush_tlb_page(NULL, vaddr);



	return (void*) vaddr;

arch/powerpc/include/asm/io.h

+1 −1
Original line number Diff line number Diff line
@@ -711,7 +711,7 @@ static inline void * phys_to_virt(unsigned long address) 
/*

 * Change "struct page" to physical address.

 */

#define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)

#define page_to_phys(page)	((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)



/* We do NOT want virtual merging, it would put too much pressure on

 * our iommu allocator. Instead, we want drivers to be smart enough

arch/powerpc/include/asm/page_32.h

+7 −1
Original line number Diff line number Diff line
@@ -13,10 +13,16 @@ 
#define ARCH_KMALLOC_MINALIGN	L1_CACHE_BYTES

#endif



#ifdef CONFIG_PTE_64BIT

#define PTE_FLAGS_OFFSET	4	/* offset of PTE flags, in bytes */

#else

#define PTE_FLAGS_OFFSET	0

#endif



#ifndef __ASSEMBLY__

/*

 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit

 * physical addressing.  For now this just the IBM PPC440.

 * physical addressing.

 */

#ifdef CONFIG_PTE_64BIT

typedef unsigned long long pte_basic_t;

arch/powerpc/include/asm/pgtable-ppc32.h

+48 −9
Original line number Diff line number Diff line
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush; 
#define _PAGE_HWEXEC	0x00000004		/* H: Execute permission */

#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */

#define _PAGE_DIRTY	0x00000010		/* S: Page dirty */

#define _PAGE_SPECIAL	0x00000020		/* S: Special page */

#define _PAGE_USER	0x00000040		/* S: User page */

#define _PAGE_ENDIAN	0x00000080		/* H: E bit */

#define _PAGE_GUARDED	0x00000100		/* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush; 
/* ERPN in a PTE never gets cleared, ignore it */

#define _PTE_NONE_MASK	0xffffffff00000000ULL



#define __HAVE_ARCH_PTE_SPECIAL



#elif defined(CONFIG_FSL_BOOKE)

/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush; 
#define _PAGE_COHERENT	0x00100	/* H: M bit */

#define _PAGE_NO_CACHE	0x00200	/* H: I bit */

#define _PAGE_WRITETHRU	0x00400	/* H: W bit */

#define _PAGE_SPECIAL	0x00800 /* S: Special page */



#ifdef CONFIG_PTE_64BIT

/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush; 
#define _PMD_PRESENT_MASK (PAGE_MASK)

#define _PMD_BAD	(~PAGE_MASK)



#define __HAVE_ARCH_PTE_SPECIAL



#elif defined(CONFIG_8xx)

/* Definitions for 8xx embedded chips. */

#define _PAGE_PRESENT	0x0001	/* Page is valid */
@@ -362,8 +367,14 @@ extern int icache_44x_need_flush; 
#define _PAGE_ACCESSED	0x100	/* R: page referenced */

#define _PAGE_EXEC	0x200	/* software: i-cache coherency required */

#define _PAGE_RW	0x400	/* software: user write access allowed */

#define _PAGE_SPECIAL	0x800	/* software: Special page */



#ifdef CONFIG_PTE_64BIT

/* We never clear the high word of the pte */

#define _PTE_NONE_MASK	(0xffffffff00000000ULL | _PAGE_HASHPTE)

#else

#define _PTE_NONE_MASK	_PAGE_HASHPTE

#endif



#define _PMD_PRESENT	0

#define _PMD_PRESENT_MASK (PAGE_MASK)
@@ -372,6 +383,8 @@ extern int icache_44x_need_flush; 
/* Hash table based platforms need atomic updates of the linux PTE */

#define PTE_ATOMIC_UPDATES	1



#define __HAVE_ARCH_PTE_SPECIAL



#endif



/*
@@ -404,6 +417,9 @@ extern int icache_44x_need_flush; 
#ifndef _PAGE_WRITETHRU

#define _PAGE_WRITETHRU	0

#endif

#ifndef _PAGE_SPECIAL

#define _PAGE_SPECIAL	0

#endif

#ifndef _PMD_PRESENT_MASK

#define _PMD_PRESENT_MASK	_PMD_PRESENT

#endif
@@ -517,7 +533,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); 


#define pte_none(pte)		((pte_val(pte) & ~_PTE_NONE_MASK) == 0)

#define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)

#define pte_clear(mm,addr,ptep)	do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)

#define pte_clear(mm, addr, ptep) \

	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)



#define pmd_none(pmd)		(!pmd_val(pmd))

#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
@@ -533,7 +550,7 @@ static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 
static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }

static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }

static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }

static inline int pte_special(pte_t pte)	{ return 0; }

static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }



static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }

static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
@@ -552,7 +569,7 @@ static inline pte_t pte_mkdirty(pte_t pte) { 
static inline pte_t pte_mkyoung(pte_t pte) {

	pte_val(pte) |= _PAGE_ACCESSED; return pte; }

static inline pte_t pte_mkspecial(pte_t pte) {

	return pte; }

	pte_val(pte) |= _PAGE_SPECIAL; return pte; }

static inline unsigned long pte_pgprot(pte_t pte)

{

	return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
@@ -575,6 +592,10 @@ extern int flush_hash_pages(unsigned context, unsigned long va, 
extern void add_hash_page(unsigned context, unsigned long va,

			  unsigned long pmdval);



/* Flush an entry from the TLB/hash table */

extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,

			     unsigned long address);



/*

 * Atomic PTE updates.

 *
@@ -612,9 +633,6 @@ static inline unsigned long pte_update(pte_t *p, 
	return old;

}

#else /* CONFIG_PTE_64BIT */

/* TODO: Change that to only modify the low word and move set_pte_at()

 * out of line

 */

static inline unsigned long long pte_update(pte_t *p,

					    unsigned long clr,

					    unsigned long set)
@@ -652,14 +670,35 @@ static inline unsigned long long pte_update(pte_t *p, 
 * On machines which use an MMU hash table we avoid changing the

 * _PAGE_HASHPTE bit.

 */

static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,



static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,

			      pte_t *ptep, pte_t pte)

{

#if _PAGE_HASHPTE != 0

#if (_PAGE_HASHPTE != 0) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)

	pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);

#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)

#if _PAGE_HASHPTE != 0

	if (pte_val(*ptep) & _PAGE_HASHPTE)

		flush_hash_entry(mm, ptep, addr);

#endif

	__asm__ __volatile__("\

		stw%U0%X0 %2,%0\n\

		eieio\n\

		stw%U0%X0 %L2,%1"

	: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))

	: "r" (pte) : "memory");

#else

	*ptep = pte;

	*ptep = (*ptep & _PAGE_HASHPTE) | (pte & ~_PAGE_HASHPTE);

#endif

}



static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,

			      pte_t *ptep, pte_t pte)

{

#if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)

	WARN_ON(pte_present(*ptep));

#endif

	__set_pte_at(mm, addr, ptep, pte);

}



/*

arch/powerpc/include/asm/reg_booke.h

+7 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */

#define SPRN_L1CSR0	0x3F2	/* L1 Cache Control and Status Register 0 */

#define SPRN_L1CSR1	0x3F3	/* L1 Cache Control and Status Register 1 */

#define SPRN_MMUCSR0	0x3F4	/* MMU Control and Status Register 0 */

#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */

#define SPRN_BUCSR	0x3F5	/* Branch Unit Control and Status */

#define SPRN_L2CSR0	0x3F9	/* L2 Data Cache Control and Status Register 0 */
@@ -410,6 +411,12 @@ 
#define L2CSR0_L2LOA	0x00000080	/* L2 Cache Lock Overflow Allocate */

#define L2CSR0_L2LO	0x00000020	/* L2 Cache Lock Overflow */



/* Bit definitions for MMUCSR0 */

#define MMUCSR0_TLB1FI	0x00000002	/* TLB1 Flash invalidate */

#define MMUCSR0_TLB0FI	0x00000004	/* TLB0 Flash invalidate */

#define MMUCSR0_TLB2FI	0x00000040	/* TLB2 Flash invalidate */

#define MMUCSR0_TLB3FI	0x00000020	/* TLB3 Flash invalidate */



/* Bit definitions for SGR. */

#define SGR_NORMAL	0		/* Speculative fetching allowed. */

#define SGR_GUARDED	1		/* Speculative fetching disallowed. */