Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-32] |    n    |

     | RES0                         | [63-48] |    n    |

     |--------------------------------------------------|

     | DP                           | [47-44] |    y    |

     |--------------------------------------------------|

     | SM4                          | [43-40] |    y    |

     |--------------------------------------------------|

     | SM3                          | [39-36] |    y    |

     |--------------------------------------------------|

     | SHA3                         | [35-32] |    y    |

     |--------------------------------------------------|

     | RDM                          | [31-28] |    y    |

     |--------------------------------------------------|

     | RES0                         | [27-24] |    n    |

     |--------------------------------------------------|

     | ATOMICS                      | [23-20] |    y    |

     |--------------------------------------------------|

     | CRC32                        | [19-16] |    y    |

     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-28] |    n    |

     | RES0                         | [63-36] |    n    |

     |--------------------------------------------------|

     | SVE                          | [35-32] |    y    |

     |--------------------------------------------------|

     | RES0                         | [31-28] |    n    |

     |--------------------------------------------------|

     | GIC                          | [27-24] |    n    |

     |--------------------------------------------------|

ARM64 ELF hwcaps

================

This document describes the usage and semantics of the arm64 ELF hwcaps.

1. Introduction

---------------

Some hardware or software features are only available on some CPU

implementations, and/or with certain kernel configurations, but have no

architected discovery mechanism available to userspace code at EL0. The

kernel exposes the presence of these features to userspace through a set

of flags called hwcaps, exposed in the auxilliary vector.

Userspace software can test for features by acquiring the AT_HWCAP entry

of the auxilliary vector, and testing whether the relevant flags are

set, e.g.

bool floating_point_is_present(void)

{

	unsigned long hwcaps = getauxval(AT_HWCAP);

	if (hwcaps & HWCAP_FP)

		return true;

	return false;

}

Where software relies on a feature described by a hwcap, it should check

the relevant hwcap flag to verify that the feature is present before

attempting to make use of the feature.

Features cannot be probed reliably through other means. When a feature

is not available, attempting to use it may result in unpredictable

behaviour, and is not guaranteed to result in any reliable indication

that the feature is unavailable, such as a SIGILL.

2. Interpretation of hwcaps

---------------------------

The majority of hwcaps are intended to indicate the presence of features

which are described by architected ID registers inaccessible to

userspace code at EL0. These hwcaps are defined in terms of ID register

fields, and should be interpreted with reference to the definition of

these fields in the ARM Architecture Reference Manual (ARM ARM).

Such hwcaps are described below in the form:

    Functionality implied by idreg.field == val.

Such hwcaps indicate the availability of functionality that the ARM ARM

defines as being present when idreg.field has value val, but do not

indicate that idreg.field is precisely equal to val, nor do they

indicate the absence of functionality implied by other values of

idreg.field.

Other hwcaps may indicate the presence of features which cannot be

described by ID registers alone. These may be described without

reference to ID registers, and may refer to other documentation.

3. The hwcaps exposed in AT_HWCAP

---------------------------------

HWCAP_FP

    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.

HWCAP_ASIMD

    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.

HWCAP_EVTSTRM

    The generic timer is configured to generate events at a frequency of

    approximately 100KHz.

HWCAP_AES

    Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0001.

HWCAP_PMULL

    Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0010.

HWCAP_SHA1

    Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.

HWCAP_SHA2

    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.

HWCAP_CRC32

    Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.

HWCAP_ATOMICS

    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.

HWCAP_FPHP

    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.

HWCAP_ASIMDHP

    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.

HWCAP_CPUID

    EL0 access to certain ID registers is available, to the extent

    described by Documentation/arm64/cpu-feature-registers.txt.

    These ID registers may imply the availability of features.

HWCAP_ASIMDRDM

    Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.

HWCAP_JSCVT

    Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.

HWCAP_FCMA

    Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.

HWCAP_LRCPC

    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.

HWCAP_DCPOP

    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.

HWCAP_SHA3

    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.

HWCAP_SM3

    Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.

HWCAP_SM4

    Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.

HWCAP_ASIMDDP

    Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.

HWCAP_SHA512

    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0002.

HWCAP_SVE

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.

 +-------------------------------------------------> [63] TTBR0/1

When using KVM, the hypervisor maps kernel pages in EL2, at a fixed

offset from the kernel VA (top 24bits of the kernel VA set to zero):

When using KVM without the Virtualization Host Extensions, the hypervisor

maps kernel pages in EL2 at a fixed offset from the kernel VA. See the

kern_hyp_va macro for more details.

Start			End			Size		Use

-----------------------------------------------------------------------

0000004000000000	0000007fffffffff	 256GB		kernel objects mapped in HYP

When using KVM with the Virtualization Host Extensions, no additional

mappings are created, since the host kernel runs directly in EL2.

* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)

ARMv8.2 introduces the optional Statistical Profiling Extension for collecting

performance sample data using an in-memory trace buffer.

** SPE Required properties:

- compatible : should be one of:

	       "arm,statistical-profiling-extension-v1"

- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where

               SPE is only supported on a subset of the CPUs, please consult

	       the arm,gic-v3 binding for details on describing a PPI partition.

** Example:

spe-pmu {

        compatible = "arm,statistical-profiling-extension-v1";

        interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;

};