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Commit c9a533f0 authored by Prakash Kamliya's avatar Prakash Kamliya Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Remove KGSL_PROP_SP_GENERIC_MEM property 



This property is not getting used in user mode driver,
retaining number in uapi header.

Change-Id: If4f90b8984d469d27c0439965f77b3a1e35f388a
Signed-off-by: default avatarPrakash Kamliya <pkamliya@codeaurora.org>
parent 4a6d5df1

drivers/gpu/msm/adreno.c

+0 −13
Original line number Diff line number Diff line
@@ -2368,18 +2368,6 @@ static int adreno_prop_uche_gmem_addr(struct kgsl_device *device, 
	return copy_prop(value, count, &vaddr, sizeof(vaddr));

}



static int adreno_prop_sp_generic_mem(struct kgsl_device *device,

		u32 type, void __user *value, size_t count)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct kgsl_sp_generic_mem sp_mem = {

		.local = adreno_dev->sp_local_gpuaddr,

		.pvt = adreno_dev->sp_pvt_gpuaddr,

	};



	return copy_prop(value, count, &sp_mem, sizeof(sp_mem));

}



static int adreno_prop_ucode_version(struct kgsl_device *device,

		u32 type, void __user *value, size_t count)

{
@@ -2447,7 +2435,6 @@ static struct { 
	[KGSL_PROP_MMU_ENABLE] = { .func = adreno_prop_s32 },

	[KGSL_PROP_INTERRUPT_WAITS] = { .func = adreno_prop_s32 },

	[KGSL_PROP_UCHE_GMEM_VADDR] = { .func = adreno_prop_uche_gmem_addr },

	[KGSL_PROP_SP_GENERIC_MEM] = { .func = adreno_prop_sp_generic_mem },

	[KGSL_PROP_UCODE_VERSION] = { .func = adreno_prop_ucode_version },

	[KGSL_PROP_GPMU_VERSION] = { .func = adreno_prop_gpmu_version },

	[KGSL_PROP_HIGHEST_BANK_BIT] = { .func = adreno_prop_u32 },

drivers/gpu/msm/adreno.h

+0 −4
Original line number Diff line number Diff line
@@ -460,8 +460,6 @@ enum gpu_coresight_sources { 
 * buffer

 * @pwrup_reglist: Memdesc holding the power up register list

 * which is used by CP during preemption and IFPC

 * @sp_local_gpuaddr: Base GPU virtual address for SP local memory

 * @sp_pvt_gpuaddr: Base GPU virtual address for SP private memory

 * @lm_fw: The LM firmware handle

 * @lm_sequence: Pointer to the start of the register write sequence for LM

 * @lm_size: The dword size of the LM sequence
@@ -534,8 +532,6 @@ struct adreno_device { 
	struct kgsl_memdesc profile_buffer;

	unsigned int profile_index;

	struct kgsl_memdesc pwrup_reglist;

	uint64_t sp_local_gpuaddr;

	uint64_t sp_pvt_gpuaddr;

	const struct firmware *lm_fw;

	uint32_t *lm_sequence;

	uint32_t lm_size;

drivers/gpu/msm/adreno_a5xx.c

+0 −6
Original line number Diff line number Diff line
@@ -142,7 +142,6 @@ static void a5xx_check_features(struct adreno_device *adreno_dev) 


static void a5xx_platform_setup(struct adreno_device *adreno_dev)

{

	uint64_t addr;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {
@@ -166,11 +165,6 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

	}



	/* Calculate SP local and private mem addresses */

	addr = ALIGN(ADRENO_UCHE_GMEM_BASE + adreno_dev->gmem_size, SZ_64K);

	adreno_dev->sp_local_gpuaddr = addr;

	adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;



	/* Setup defaults that might get changed by the fuse bits */

	adreno_dev->lm_leakage = A530_DEFAULT_LEAKAGE;

	adreno_dev->speed_bin = 0;

drivers/gpu/msm/adreno_a6xx.c

+0 −6
Original line number Diff line number Diff line
@@ -2786,14 +2786,8 @@ static void a6xx_check_features(struct adreno_device *adreno_dev) 
}

static void a6xx_platform_setup(struct adreno_device *adreno_dev)

{

	uint64_t addr;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	/* Calculate SP local and private mem addresses */

	addr = ALIGN(ADRENO_UCHE_GMEM_BASE + adreno_dev->gmem_size, SZ_64K);

	adreno_dev->sp_local_gpuaddr = addr;

	adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;



	if (adreno_has_gbif(adreno_dev)) {

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs =

				a6xx_perfcounters_gbif;