Loading drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v150_100.h +3 −3 Original line number Diff line number Diff line Loading @@ -381,7 +381,7 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -431,11 +431,11 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ .value = 1, .value = 0x5, }, }, { Loading Loading
drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v150_100.h +3 −3 Original line number Diff line number Diff line Loading @@ -381,7 +381,7 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -431,11 +431,11 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ .value = 1, .value = 0x5, }, }, { Loading