Merge "msm: kgsl: Add A504 GPU support for SDM429" (c966e916) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/gpu/msm/adreno-gpulist.h

+15 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -201,6 +201,20 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
		.max_power = 5448,
		.regfw_name = "a530v3_seq.fw2",
		},
		{
		.gpurev = ADRENO_REV_A504,
		.core = 5,
		.major = 0,
		.minor = 4,
		.patchid = ANY_ID,
		.features = ADRENO_PREEMPTION \| ADRENO_64BIT,
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		.gpudev = &adreno_a5xx_gpudev,
		.gmem_size = (SZ_128K + SZ_8K),
		.num_protected_regs = 0x20,
		.busy_mask = 0xFFFFFFFE,
		},
		{
		.gpurev = ADRENO_REV_A505,
		.core = 5,

drivers/gpu/msm/adreno.h

+5 −3

Original line number	Diff line number	Diff line
		/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -212,6 +212,7 @@ enum adreno_gpurev {
		ADRENO_REV_A418 = 418,
		ADRENO_REV_A420 = 420,
		ADRENO_REV_A430 = 430,
		ADRENO_REV_A504 = 504,
		ADRENO_REV_A505 = 505,
		ADRENO_REV_A506 = 506,
		ADRENO_REV_A508 = 508,
		@@ -1274,6 +1275,7 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev)
		ADRENO_GPUREV(adreno_dev) < 600;
		}

		ADRENO_TARGET(a504, ADRENO_REV_A504)
		ADRENO_TARGET(a505, ADRENO_REV_A505)
		ADRENO_TARGET(a506, ADRENO_REV_A506)
		ADRENO_TARGET(a508, ADRENO_REV_A508)
		@@ -1300,9 +1302,9 @@ static inline int adreno_is_a530v3(struct adreno_device *adreno_dev)
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2);
		}

		static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev)
		static inline int adreno_is_a504_to_a506(struct adreno_device *adreno_dev)
		{
		return ADRENO_GPUREV(adreno_dev) >= 505 &&
		return ADRENO_GPUREV(adreno_dev) >= 504 &&
		ADRENO_GPUREV(adreno_dev) <= 506;
		}

drivers/gpu/msm/adreno_a5xx.c

+7 −3

Original line number	Diff line number	Diff line
		@@ -56,6 +56,7 @@ static const struct adreno_vbif_platform a5xx_vbif_platforms[] = {
		{ adreno_is_a512, a540_vbif },
		{ adreno_is_a510, a530_vbif },
		{ adreno_is_a508, a530_vbif },
		{ adreno_is_a504, a530_vbif },
		{ adreno_is_a505, a530_vbif },
		{ adreno_is_a506, a530_vbif },
		};
		@@ -127,6 +128,7 @@ static const struct {
		} a5xx_efuse_funcs[] = {
		{ adreno_is_a530, a530_efuse_leakage },
		{ adreno_is_a530, a530_efuse_speed_bin },
		{ adreno_is_a504, a530_efuse_speed_bin },
		{ adreno_is_a505, a530_efuse_speed_bin },
		{ adreno_is_a512, a530_efuse_speed_bin },
		{ adreno_is_a508, a530_efuse_speed_bin },
		@@ -152,7 +154,7 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev)
		uint64_t addr;
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		if (adreno_is_a505_or_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev)) {
		if (adreno_is_a504_to_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev)) {
		gpudev->snapshot_data->sect_sizes->cp_meq = 32;
		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;
		gpudev->snapshot_data->sect_sizes->roq = 256;
		@@ -1181,6 +1183,7 @@ static const struct {
		{ adreno_is_a530, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },
		{ adreno_is_a512, a512_hwcg_regs, ARRAY_SIZE(a512_hwcg_regs) },
		{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },
		{ adreno_is_a504, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
		{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
		{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
		{ adreno_is_a508, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },
		@@ -1930,7 +1933,7 @@ static void a5xx_start(struct adreno_device *adreno_dev)
		* Below CP registers are 0x0 by default, program init
		* values based on a5xx flavor.
		*/
		if (adreno_is_a505_or_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev)) {
		if (adreno_is_a504_to_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev)) {
		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);
		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);
		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
		@@ -1956,7 +1959,7 @@ static void a5xx_start(struct adreno_device *adreno_dev)
		* vtxFifo and primFifo thresholds default values
		* are different.
		*/
		if (adreno_is_a505_or_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev))
		if (adreno_is_a504_to_a506(adreno_dev) \|\| adreno_is_a508(adreno_dev))
		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,
		(0x100 << 11 \| 0x100 << 22));
		else if (adreno_is_a510(adreno_dev) \|\| adreno_is_a512(adreno_dev))
		@@ -2264,6 +2267,7 @@ static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev)
		switch (ADRENO_GPUREV(adreno_dev)) {
		case ADRENO_REV_A510:
		return 0x00000001; /* Ucode workaround for token end syncs */
		case ADRENO_REV_A504:
		case ADRENO_REV_A505:
		case ADRENO_REV_A506:
		case ADRENO_REV_A530: