iommu: smmu: Defer SMR mask discovery after writes to SCR0

The format of the SMR register depends on the value of 
SCR0.EXIDENABLE bit. With the support for Extended Stream
ID now available, defer the SMR mask testing after SCR0
register is written.

Change-Id: Iafdd6c38be5c0cd4be2f6f53c50853c308226c26
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>