Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c696b445 authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: Add display clock driver for TRINKET 



Add support for the display clock controller found on
TRINKET based devices. This would allow display device
drivers to probe and control their clocks.

Change-Id: I20c294ec2cfa7eced3c677bd84027af27d3a6cb9
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 62e31c6d

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

+2 −1
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ Required properties : 
		"qcom,dispcc-sm8150",

		"qcom,dispcc-sm8150-v2",

		"qcom,dispcc-sm6150",

		"qcom,dispcc-sdmmagpie".

		"qcom,dispcc-sdmmagpie",

		"qcom,dispcc-trinket".

- reg : Shall contain base register location and length.

- reg-names: Address name. Must be "cc_base".

- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -529,3 +529,12 @@ config SM_VIDEOCC_TRINKET 
	  TRINKET devices.

	  Say Y if you want to support video devices and functionality such as

	  video encode/decode.



config SM_DISPCC_TRINKET

	tristate "TRINKET Display Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the display clock controller on Qualcomm Technologies, Inc

	  TRINKET devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o 
obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o

obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o

obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o

obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o

obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o

obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o

obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o

drivers/clk/qcom/dispcc-trinket.c

0 → 100644
+798 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,dispcc-trinket.h

+31 −20
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -11,25 +11,36 @@ 
 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_TRINKET_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_TRINKET_H

#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_TRINKET_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_TRINKET_H



/* GPUCC clock registers */

#define GPU_CC_PLL0_OUT_AUX2			0

#define GPU_CC_PLL1_OUT_AUX2			1

#define GPU_CC_CRC_AHB_CLK			2

#define GPU_CC_CX_APB_CLK			3

#define GPU_CC_CX_GFX3D_CLK			4

#define GPU_CC_CX_GFX3D_SLV_CLK			5

#define GPU_CC_CX_GMU_CLK			6

#define GPU_CC_CX_SNOC_DVM_CLK			7

#define GPU_CC_CXO_AON_CLK			8

#define GPU_CC_CXO_CLK				9

#define GPU_CC_GMU_CLK_SRC			10

#define GPU_CC_SLEEP_CLK			11

#define GPU_CC_GX_CXO_CLK			12

#define GPU_CC_GX_GFX3D_CLK			13

#define GPU_CC_GX_GFX3D_CLK_SRC			14

#define GPU_CC_AHB_CLK				15

#define DISP_CC_PLL0_OUT_MAIN					0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_DP_AUX_CLK					6

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				7

#define DISP_CC_MDSS_DP_CRYPTO_CLK				8

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				9

#define DISP_CC_MDSS_DP_LINK_CLK				10

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				11

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				12

#define DISP_CC_MDSS_DP_PIXEL_CLK				13

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				14

#define DISP_CC_MDSS_ESC0_CLK					15

#define DISP_CC_MDSS_ESC0_CLK_SRC				16

#define DISP_CC_MDSS_MDP_CLK					17

#define DISP_CC_MDSS_MDP_CLK_SRC				18

#define DISP_CC_MDSS_MDP_LUT_CLK				19

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				20

#define DISP_CC_MDSS_PCLK0_CLK					21

#define DISP_CC_MDSS_PCLK0_CLK_SRC				22

#define DISP_CC_MDSS_ROT_CLK					23

#define DISP_CC_MDSS_ROT_CLK_SRC				24

#define DISP_CC_MDSS_VSYNC_CLK					25

#define DISP_CC_MDSS_VSYNC_CLK_SRC				26

#define DISP_CC_XO_CLK						27



#endif