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Commit c588598d authored by Ravikishore Pampana's avatar Ravikishore Pampana Committed by Gerrit - the friendly Code Review server
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msm: camera: isp: Poll for CSID hardware reset status 



Currently after csid hardware reset, software wait for interrupt to come.
CSID irq handler gives the complete signal once CSID reset irq raised.
Instead of waiting for reset irq comes, software can poll reset status
register and check status. This avoids the race conditions in the csid
irq complete signals.

Change-Id: Ibe0ea7bbb5efe89ea38e095371b60bfcbc34c0e3
Signed-off-by: default avatarRavikishore Pampana <rpampana@codeaurora.org>
parent 8cb8ef8b

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+24 −24
Original line number Diff line number Diff line
@@ -1064,10 +1064,6 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) 
	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_irq_cmd_addr);



	/* Enable the top IRQ interrupt */

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

			csid_reg->cmn_reg->csid_top_irq_mask_addr);



	val = cam_io_r_mb(soc_info->reg_map[0].mem_base +

			csid_reg->cmn_reg->csid_hw_version_addr);

	CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x",
@@ -2299,25 +2295,38 @@ static int cam_ife_csid_reset_retain_sw_reg( 
	struct cam_ife_csid_hw *csid_hw)

{

	int rc = 0;

	uint32_t status;

	const struct cam_ife_csid_reg_offset *csid_reg =

		csid_hw->csid_info->csid_reg;

	struct cam_hw_soc_info          *soc_info;



	soc_info = &csid_hw->hw_info->soc_info;

	/* clear the top interrupt first */

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_clear_addr);

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_irq_cmd_addr);



	init_completion(&csid_hw->csid_top_complete);

	cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb,

		csid_hw->hw_info->soc_info.reg_map[0].mem_base +

		soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_rst_strobes_addr);



	CAM_DBG(CAM_ISP, " Waiting for SW reset complete from irq handler");

	rc = wait_for_completion_timeout(&csid_hw->csid_top_complete,

		msecs_to_jiffies(IFE_CSID_TIMEOUT));

	if (rc <= 0) {

		CAM_ERR(CAM_ISP, "CSID:%d reset completion in fail rc = %d",

	rc = readl_poll_timeout(soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_status_addr,

			status, (status & 0x1) == 0x1,

		CAM_IFE_CSID_TIMEOUT_SLEEP_US, CAM_IFE_CSID_TIMEOUT_ALL_US);

	if (rc < 0) {

		CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d",

			  csid_hw->hw_intf->hw_idx, rc);

		if (rc == 0)

		rc = -ETIMEDOUT;

	} else {

		CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d",

			csid_hw->hw_intf->hw_idx, rc);

		rc = 0;

	}

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_clear_addr);

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_irq_cmd_addr);



	return rc;

}
@@ -2735,8 +2744,6 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
		csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr);



	/* clear */

	cam_io_w_mb(irq_status_top, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_clear_addr);

	cam_io_w_mb(irq_status_rx, soc_info->reg_map[0].mem_base +

		csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr);

	if (csid_reg->cmn_reg->num_pix)
@@ -2762,13 +2769,6 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
	CAM_DBG(CAM_ISP, "irq_status_rdi1= 0x%x", irq_status_rdi[1]);

	CAM_DBG(CAM_ISP, "irq_status_rdi2= 0x%x", irq_status_rdi[2]);



	if (irq_status_top) {

		CAM_DBG(CAM_ISP, "CSID global reset complete......Exit");

		complete(&csid_hw->csid_top_complete);

		return IRQ_HANDLED;

	}





	if (irq_status_rx & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) {

		CAM_DBG(CAM_ISP, "csi rx reset complete");

		complete(&csid_hw->csid_csi2_complete);