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Commit c446a999 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add MHI SoC reset offset"

parents af686fab 6d71c122

Documentation/devicetree/bindings/pci/msm_ep_pcie.txt

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ Optional Properties: 
	- qcom,msm-bus,num-paths

	- qcom,msm-bus,vectors-KBps

  - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode.

  - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset.



Example:

arch/arm64/boot/dts/qcom/sdxprairie.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1234,6 +1234,7 @@ 
		qcom,pcie-aggregated-irq;

		qcom,pcie-mhi-a7-irq;

		qcom,phy-status-reg = <0x814>;

		qcom,mhi-soc-reset-offset = <0xb01b8>;



		qcom,phy-init = <0x1240 0x001 0x0 0x1

				0x100c 0x002 0x0 0x1

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+3 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ 
#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0

#define PCIE20_L1SUB_CAPABILITY        0x154

#define PCIE20_L1SUB_CONTROL1          0x158

#define PCIE20_BUS_DISCONNECT_STATUS   0x68c

#define PCIE20_ACK_F_ASPM_CTRL_REG     0x70C

#define PCIE20_MASK_ACK_N_FTS          0xff00

#define PCIE20_MISC_CONTROL_1          0x8BC
@@ -367,10 +368,12 @@ struct ep_pcie_dev_t { 
	bool                         pcie_edma;

	bool                         tcsr_not_supported;

	bool			     m2_autonomous;

	bool			     mhi_soc_reset_en;

	u32                          dbi_base_reg;

	u32                          slv_space_reg;

	u32                          phy_status_reg;

	u32                          phy_init_len;

	u32			     mhi_soc_reset_offset;

	struct ep_pcie_phy_info_t    *phy_init;

	bool                         perst_enum;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+26 −0
Original line number Diff line number Diff line
@@ -607,6 +607,19 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
								0, BIT(0));

	}



	/* Update offset to AXI address for Host initiated SOC reset */

	if (dev->mhi_soc_reset_en) {

		EP_PCIE_DBG(dev,

			"PCIe V%d: Updating SOC reset offset with val:0x%x\n",

				dev->rev, dev->mhi_soc_reset_offset);

		ep_pcie_write_reg(dev->parf, PCIE20_BUS_DISCONNECT_STATUS,

				dev->mhi_soc_reset_offset);

		val = readl_relaxed(dev->parf +

					PCIE20_BUS_DISCONNECT_STATUS);

		EP_PCIE_DBG(dev,

			"PCIe V%d:SOC reset offset val:0x%x\n", dev->rev, val);

	}



	if (!configured) {

		/* Configure PCIe to endpoint mode */

		ep_pcie_write_reg(dev->parf, PCIE20_PARF_DEVICE_TYPE, 0x0);
@@ -3121,6 +3134,19 @@ static int ep_pcie_probe(struct platform_device *pdev) 
		"PCIe V%d: MHI M2 autonomous is %s enabled\n",

		ep_pcie_dev.rev, ep_pcie_dev.m2_autonomous ? "" : "not");



	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,mhi-soc-reset-offset",

				&ep_pcie_dev.mhi_soc_reset_offset);

	if (ret) {

		EP_PCIE_DBG(&ep_pcie_dev,

			"PCIe V%d: qcom,mhi-soc-reset does not exist\n",

			ep_pcie_dev.rev);

	} else {

		EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: soc-reset-offset:0x%x\n",

			ep_pcie_dev.rev, ep_pcie_dev.mhi_soc_reset_offset);

		ep_pcie_dev.mhi_soc_reset_en = true;

	}



	memcpy(ep_pcie_dev.vreg, ep_pcie_vreg_info,

				sizeof(ep_pcie_vreg_info));

	memcpy(ep_pcie_dev.gpio, ep_pcie_gpio_info,